JP2692439B2 - Integrated circuit binary memory cell - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor
Monolithic semiconductor chips using transistor technology
Random access memory (RA)
M), in particular, from the drain power supply node to the memory cell
Of insulated gate field effect transistor (IGFET)
Impedance for conducting extremely low current flowing to the channel
An integrated circuit binary memory cell having a dance device
You. [0002] 2. Description of the Related Art Digital memory is a computer to be stored.
Two external signals for each bit of
Separate physical memory that can be set to one of two different states
You must have a cell. The cell is set
Left indefinitely, or to other external signals
Therefore, the set state is maintained until it can be changed to another state
There is a need to. Two different states of a memory cell are
Nature that does not require an external energy source to be maintained in its natural state
It can be a developmental state. In addition,
Volatile memory device requiring external bias to hold
It is also possible to use Of such memory devices
A well-known example is a bistable circuit using a semiconductor device. these
This device causes the stored information to deteriorate or be completely lost.
Continuous power supply, i.e.
Continuous power supply is required. [0003] Large-scale integrated circuit (LSI) technology has
Large scale of such memory elements on a single chip of Recon
Arrays are now configured. Typically MOS technology
These memory cells have a normal bistable structure
Consisting of multi-component circuits. Semiconductor bistable elements
This type of note requires a constant power supply for holding
Li is essentially a volatile memory. In some applications,
Data is not irretrievably lost due to power interruption
That is essentially important. In those cases, the battery
DC power is cut off unexpectedly
The battery supplies power to the power node of the memory device.
Memory to operate in standby mode
Power may be supplied during the operation. The direct advantage of semiconductor memory devices is that
High power and low power requirements. This application
In the field, insulated gate MOS transistors are particularly
It has been used because it requires the board area
Small, thus increasing packing density and, in addition, extremely low power consumption
This is because you can work with the bell. Utilizing IGFET
Known memory cell circuits include U.S. Pat. No. 3,967,2.
There is a cross-coupled inverter stage disclosed in No. 52.
In that circuit, both gates of a pair of MOSFETs are
Cross-coupled with true and complement data nodes
You. The information stored in the cell is
Is held. I.e. impeder
The sensing device is connected to the data node to
Keeps the gate voltage at a predetermined level corresponding to the logic content of the cell
I do. Each inverter in the cell has a driving transistor and a load
And an impedance device. Patents referenced above
In the circuit shown in
The device includes a MOSFET. In earlier circuits,
Typically, an ins having a diffusion resistance of 10 to 20 Ω / □
A pedestal device was used. But MOSFE
T can give 20,000 Ω / □, 100,
Give a practical resistance value of about 000 to 200,000Ω
MOSFET can be used because it can be obtained
I'm getting up. Using a smaller surface area than conventional diffusion resistance
Also according to MOS technology on a single monolithic chip the other
A more complicated circuit can be realized than by the method. Low
In applications to current load devices, depletion MOS
When the gate of the FET is connected to the source, the occupied substrate area is small.
It will be cheap. However, in the application to extremely low current load,
Depletion transistor with gate connected to source
Is 6.45 × in the load range of microamperes
10^-Fourmm^Two It occupies several times the area of (1 square mil). As shown in US Pat. No. 3,967,252.
Static random access memory cells
Has two cross-coupled inverters and two transfer resistors.
Resistance, that is, two load devices and four transistors
Exist. In a 1K static RAM, 102
Four memory cells occupy about 40% of total chip area
However, in a 4K static RAM, 4096
Cells account for only a small percentage of the chip
No. Minimize chip area and power consumption
In order to reduce the size of the inverter as much as possible,
The two loading devices in the Koussel have a relatively small area and
It must use low current. As a load device
Lack of depletion transistors
The dots are reversed as the physical size of the active area decreases.
Substrate effects due to gate bias generally increase
is there. Another one of using MOS device as load resistance
Two drawbacks are related to the reverse bias voltage from the source to the substrate.
Due to the substrate effect, the resistance of the MOS device is basically limited.
Is to be done. This device is 100KΩ to 200
Gives a practical resistance value of about KΩ, but has extremely low power consumption
In some applications, in the range of 1 MΩ to 100 MΩ
It is desirable to use a load device that exhibits resistance. [0007] SUMMARY OF THE INVENTION The present invention relates to a conventional MO.
Much larger than the resistance provided by the S load
An extremely low current load device that exhibits high resistance
Occupies a small surface area and is adversely affected by reverse bias conditions
Integrated circuit 2 with extremely low current load device
It is intended to provide a base memory cell. [0008] According to the present invention, a dray
Source power supply node and source power supply node
First and second data input / output nodes and insulated gate field effect
Fruit-shaped first and second transistors are provided,
Each channel of the first and second transistors is a husband
The corresponding first and second data input / output nodes
It can be electrically connected to the source power node.
And the gate of the first transistor is the second data
The second transistor is electrically connected to the input / output node.
The gate of the transistor is electrically connected to the first data input / output node.
In integrated circuit binary memory cells connected in series,
The first and second data input / output nodes are connected to the drain, respectively.
First and second impedances electrically connected to the power supply node
A dance device is installed and each impedance device
The device has a substrate of semiconductor material defining a conductive path,
The substrate is doped with extrinsic impurities with a substantially intrinsic region.
And a doped region that is
The intrinsic-extrinsic junction is defined by the boundary between the region and the doped region.
And each impedance device is
Direct connection between the power supply node and the corresponding data input / output node.
Forming a column electrical path and powering the memory cell
Minimum resistance value and previous determined based on the maximum allowable cost
Note: Determined based on the maximum predicted leakage current of the memory cell.
Is set to a resistance value in the range between the maximum resistance value
An integrated circuit binary memory cell is provided
You. According to one aspect of the present invention, the present invention provides each binary logic state.
And the true data that gives the DC impedance path corresponding to
Relationship with a binary memory cell having an input / output node for numerical data
It is carried out in the ream. This memory cell has more data
Channel that electrically connects the node to the source power node
First and second insulated gate field effect transistors having
It has a star (IGFET). Of those transistors
The gate is electrically cross-coupled to the data node.
These data nodes have first and second drain power supply nodes.
A first and a first electrically connected respectively to a second data node
Two impedance devices for each binary logic state
Is charged to the reference voltage corresponding to. Each impedance
The device is a substantially pure intrinsic semiconductor material and its intrinsic semiconductor
Boundary with extrinsic impurity diffusion region located in material region
Semiconductor structure with intrinsic-extrinsic junction created by field
It is made. Intrinsic semiconductor material is the same single semiconductor type as the substrate
However, the magnitude of its conductivity depends on the extrinsic semiconductor material.
Substantially smaller. Extrinsic semiconductor material is N type or P type
May be. Typical drain power supply voltage V_DDValue of (eg
For example, for DC 5V, total leakage of each cross-coupled transistor
Leakage currents are in the picoampere range, but
The current conducted by the combined impedance device is
In range of pairs. Therefore, this low current load impeder
The sensing device has sufficient resistance to leakage at the P-N junction in the memory cell.
It can provide a current that overcomes the
It can hold the logical contents of the cell. This
The temperature coefficient of the impedance device is the temperature of the memory cell junction.
Low current because it is characterized by having the same polarity as the frequency coefficient
The load device is the temperature of the leakage current of the memory cell transistor.
You will be "tracking" the changes. Therefore, the memory cell
The power consumed by the
Can be designed to be a minimum value. Conventional high
Depending on the resistance diffusion resistance, the minimum current in the same temperature range
Note that no flow design is possible. The reason
Is the leakage current in the drain of the memory cell transistor
The conventional diffusion resistance flows while the flow increases with temperature.
This is because the applied current decreases. According to the present invention, the surface of the insulating layer is substantially
By depositing a layer of intrinsic semiconductor material on the
The load device is configured, and thereby the drain of the IGFET
Conductive interconnection between the diffusion node and the drain power node
You can continue. Form on selected surface areas of the intrinsic interconnect layer.
Exposed through the mask made
Intrinsic semiconductor material underneath the living area converts to extrinsic conductivity type
Drain diffusion by diffusing impurities until
True at the selected position midway between the drain node and the drain power node.
A sex-exogenous junction is formed. In a preferred embodiment, each impedance is
Equipment is in the isoplanar silicon gate process.
One of the data nodes with the drain power supply node selected
Part of polysilicon strip interconnecting to
Formed as. The part of the polycrystalline silicon strip
Extends from the selected data node to that data node
Form cross-coupled gates. DC current due to intrinsic-extrinsic junction of silicon
The impedance approaches 1,000 MΩ at reverse bias.
This impedance allows relatively small amounts of impurities to be intrinsic semiconductors.
Through the region, extrinsic regions that are lightly doped in that region
Can be reduced by spreading until converted to
it can. According to this method, the intrinsic-exogenous junction is highly concentrated.
Impurity regions form junctions with relatively low-concentration impurity regions
Extrinsic-outside characterized by being arranged in a relationship
Converted to intrinsic junction. In that case, both impurity concentrations are the same
It may be a conductive type or a reverse conductive type. [0013] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
Fabricated on a single monolithic chip using
This will be described in combination with a RAM of a different type. Disclosed here
Is a structure that can be manufactured on a single semiconductor chip.
And is primarily intended for such fabrication. FIGS. 1 and 2 show an arrangement according to the invention.
A part of the RAM using the illustrated circuit is shown. A part of the RAM shown in FIG.
Having memory cells 10 which are conventionally operated in rows.
Of an array of many such cells arranged in rows
Part. The memory cells 10 are arranged in the same column and have complementary data.
Data bus D, D Is joined to. (In addition, after English letters
Underline represents its complement, and overline
Is the same meaning as. ) The memory cells 10 are arranged in different rows.
So that these cells are on different row lines RA₁
And RA_Two Addressable or operable by
To be Row address line RA₁ Is all the notes in the first line
Enables resell and row address line RA_Two Is in the second row
Enables all memory cells. Detection amplifier and level
The lucifer is designated as a whole by reference numeral 12.
Column buses D and D It is connected to the. Detection amplifier
12 is of any conventional type, such as US Pat.
It may be that disclosed in No. 7,252. Write control times
Paths 14 and 16 are connected in the normal manner during the write cycle.
Row buses D and D It is connected to drive.
Different column buses with column enabler (not shown)
May be connected to a single sense amplifier,
Also, provide a separate sense amplifier for each column bus pair.
Is also good. FIG. 2 shows an electrical schematic diagram of the memory cell 10.
You. The binary memory cell 10 receives the first and second complementary data.
Has output nodes 1 and 2 which are binary
DC impedance path and ratio corresponding to each physical condition
Create a direct current impedance path of relatively high impedance
ing. First and second impedance devices R₁ And R
_Two Is the drain power supply node V_DDThe first and second data
Connect to do 1 and 2, respectively. Impedance device R₁ And
And R_Two Will be described later in detail. Memory cell 1
0 is a further pair of cross-coupled insulated gate field effect transistors
Transistor Q₁ And Q_Two have. Data node
1 and 2 are transistor Q₁ And Q_Two By the gate of
Cross-coupled and enable transistors Q respectively_Three You
And Q_Four By row buses D and D respectively Connected to
I have. Enable transistor Q_ThreeAnd Q_Four The gate of
Corresponding row address line RA₁ It is connected to the. Tran
Jista Q₁ And Q_Two And Q_Two Between the drain and source terminals
Each channel is in its respective data node when it is conducting
1 and 2 are source power supply node V_ssElectrically connected to To understand the operation of the circuit of FIG.
Dress line RA₁ Is at a low level (at logical "0"
Row address line RA₁ Memory cell 1 connected to
0 enabling transistor Q_Three And Q_Four Is off
Assume that As a result, in this device
Column buses D and D Is a voltage level less than one threshold
V_DDCan be taken. The reason is that the source voltage V_ss
This is because no current path exists. Typical circuit
And V_DDShould be 5V and the threshold should be about 2.5V,
In that case the column buses D and D Becomes about 2.5V. Other equipment
D and D Is V_DDVoltage level as high as
Bell or V_ssSame as or V_ssMore than
Takes a voltage level slightly higher than one threshold. This state
Now, the column buses D and D No current flows. The reason
Has no current path through the enabled cells
This is because the bus becomes an open circuit. As a result, data output
Nodes 1 and 2 are V from nodes 1 and 2, respectively_ssUp to
Substantially V respectively_DDOr V_ssTo have a voltage equal to
become. A logical "0" is stored in memory cell 10.
And the transistor Q₁ Is turned on
Data node 1 is substantially V_ssIn the transistor Q
_Two Data node 2 is substantially V_DD
Assume that In this case, row address line RA₁
Becomes high, that is, corresponds to logical "1"
When charged to voltage, transistor Q_Three , Q_Four Is on
Memory cell 10 is enabled as it enters
You. Thereby, the transistor Q₁ And Q_Three , And
And V via the row bus D_ssA current path leading to is formed. Tiger
Transistor Q_Two Is in the off state, so that the column bus D From
There is no current path to the ground. As a result, the data
Node 2 is substantially V_DDThat is, while the voltage is maintained at 5 V,
Up to. If logical "1" is address memory
If stored in cell 10, transistor Q₁ Is off
State, transistor Q_Two Is in the ON state. That
If so, Q_Two And Q_Four Current passing through the bus D About
5V to low level, column bus D and data
Node 1 is held at a precharge level of 5V. The data output nodes 1 and 2 are logically inside the cell.
According to Y_DDAnd V_ssTake one of the values these
Voltage level is to maintain the logical content of cell 10.
Must be retained. This in memory cell 10
The reference voltage from
De V_DDImpedance device R connected to₁ And R
_Two Is held in the data nodes 1 and 2. Next, FIGS. 3 and 4 show the substrate of the memory cell 10.
2 shows the arrangement. According to the present invention, a load impeder
Sensing device R₁ And R_Two Each define a first conductive path 22.
A substantially pure intrinsic semiconductor material substrate 20 and a second
Of the intrinsic semiconductor material substrate 20 defining the conductive paths 24 of the
And a diffusion region of extrinsic conductive impurities disposed therein.
The extrinsic conductive path 24 and the undoped intrinsic conductive path (true
Intrinsic-extrinsic contact depending on the interface with the semiconductor semiconductor region 22.
A joint 28 is formed. Intrinsic conduction path 22 and extrinsic conduction path 2
4 is the drain power supply node V_DDCorresponding data from
A series current path up to terminals 1 and 2 is formed. Used here
The term "intrinsic semiconductor material" refers to undoped
Diffuse or implant impurities that are simple semiconductor materials
Shall mean a single semiconductor material that has never been exposed to
You. The memory cell 10 is an extrinsic semiconductor of the first conductivity type.
Disposed on a substrate 30 of a body material, for example, a P-type single crystal silicon.
Is placed. Each field effect transistor Q₁ ~ Q_Four Is the opposite
A source region (not shown) made of a conductive type, for example, an N-type material
And a drain region (not shown).
These regions are formed in the active region 36 of the substrate 30 by a usual method.
Extend substantially parallel to each other. The insulating layer 38 is
It is arranged on the surface of the plate 30 and directly above the active area 36.
In addition, the gate region 40 is formed relatively thin. External cause
The conductive path 24 is provided for the transistor formed on the active region.
It forms the gate interconnect. The semiconductor material forming the conductive layer 20 is the substrate 3
The same single semiconductor type as polycrystalline silicon
It is preferred to be constituted as a continuous layer. Conductive layer 20
The extrinsic impurities diffused in may be N-type or P-type.
In the preferred embodiment, extrinsic impurities diffused into conductive layer 20
Is of a conductivity type opposite to the conductivity type of the substrate 30.
You. For example, for the P-type substrate 30, the conductive layer 20 is diffused.
Since the impurities to be formed are N-type, the extrinsic conductive path 24 is formed
Gate strip (abbreviated as gate strip 24)
), Source and drain regions and impeders
Sensing device R₁ , R_Two Are all isoplanar silicon games
Can be formed in one diffusion stage of the process. Next, referring to FIG. 5 and FIG.
Mode V_DDIs the diffusion gate interconnect as shown in FIG.
Having a metal adherend 42 directly bonded to the connecting portion 43
It may be. Or in some cases as shown in FIG.
The metal deposit 42 defines a first conductive path,
Directly adhered to the intrinsically pure intrinsic semiconductor region 22
Is also good. Either of the structures shown in FIGS. 5 and 6
Even if the impedance load device R_Two For
The surface area of the substrate used is extremely small,
A typical width for a 4 gate interconnect is 5μ.
The typical length of the unconducted intrinsic conductive path 22 is 8 μm.
is there. Intrinsic-extrinsic joining device formed with these dimensions
Is a large impedance of 1,000 MΩ against DC
Indicating the resistance. A relatively small amount of impurity 47 is added to intrinsic conductive path 22.
Extrinsic conductivity region whose region is very lightly doped
By spreading until it is converted to
-Dance can be reduced. With high concentration impurity regions
It is arranged so that a relatively low concentration impurity region forms a junction.
Extrinsic-extrinsic characterized by being placed
In the joining device, the impurity concentrations of both are of the same conductivity type.
Or of the opposite conductivity type, examples of which are
7 (A), (B), FIGS. 8 (A), (B), FIG.
(A), (B) and FIGS. 10 (A), (B).
You. Referring again to FIGS. 3 and 4, the substrate 30 is
It forms the starting material for the steps for carrying out the invention. semiconductor
A typical substrate 30 is silicon, and the conductivity type is N.
It may be a shape or a P shape. However, the semiconductor substrate 30 has an insulating gate.
Used in the fabrication of semiconductor field effect transistor devices.
It can be any conventional type of
The orientation and doping levels are well known and normal.
is there. In the following discussion, P-type impurities are doped.
Single-crystal silicon substrate chip
N channels by isoplanar silicon gate process
In order to construct a tunnel insulated gate transistor,
Uses a substrate chip with an impurity of the opposite conductivity type diffused in the part
The method will be described. The semiconductor substrate 30 is placed in a normal oxidation furnace.
A typical thickness of 600 ° on the surface of the substrate 30.
An oxide layer 38 is grown thermally. Then that oxide
An approximately 600 ° thick nitride layer is deposited on the layer. Next
The photoresist on the combined nitride and oxide layers
After the mask has been formed, it is processed by normal photolithographic techniques.
The mask is patterned and thereby the active area
36 and a mask defining the surrounding field area
Wear. The nitride layer is removed from the field region and
Implanted with ionic impurities of the same conductivity type as the substrate doping
I will. This ion is BF for P-type substrate_Three Such as
Can be removed from the boron compound and the N-type substrate
PH to make_Four To remove from phosphorus compounds such as
Can be. Equipment for ion implantation in that case is commercially available
And its usage is well-known industrially.
Are known. This ion implantation process step is performed in the active region 3
To the field area around 6 and
Therefore, crosstalk between adjacent transistors in the same substrate
Is reduced. The photoresist mask is removed from the active area.
When removed, there is then about 8 thermal oxide layers on the field regions.
It is grown to a thickness of 000Å. Then nitride and acid
Both oxide layers are removed from the active region and gate oxide layer 40
Are grown on the active region 36 to a thickness of about 900Å. Next, the undoped polycrystalline silicon
Intrinsic semiconductor material layer 20 (hereinafter abbreviated as polycrystalline silicon layer)
Is deposited on the gate oxide. Polycrystalline silicon layer
20 is a suitable conventional method, for example, a cold wall epitaxial reaction.
SiH in reactor or hot wall furnace_Four (Silane)
It can be formed by a solution or the like. Polycrystalline silico
Typical thickness of the insulating layer 20 is 3,000 to 6,000.
It is 0Å. Undoped polycrystalline silicon layer 20
Is masked and photoresist treated to
Group 24 is defined. Undoped gate interconnect
A diffusion barrier layer of nitride or oxide is deposited on the continuation,
It is masked and processed by photoresist.
Low current load impedance, eg R₁ Or R_Twoof
Mask 44 is defined over the location of intrinsic conductive path 22 for
You. Next, undoped polycrystalline silicon
The layers of layer 20 and active region 36 are conductive
Undergoes impurity diffusion in the form of an impurity, thereby causing impurities to be gated
Activity on both sides of strip 24 and its gate strip.
The diffusion gate and the diffusion saw
And diffusion drain regions (not shown) are formed.
You. The non-diffusion channel region is not
The gate strip is masked by the
Formed in the active region under the pump. Intrinsic-exogenous junction 28
Is the undoped portion below the mask 44 of the polycrystalline silicon layer 20.
Semiconductor material region 22 and impurity diffusion region adjacent thereto
Formed at the boundary with Next, about 10,000 Å on the chip area
A thick insulating oxide layer is formed and masked on the photoresist
Process to form conductive interconnects.
It is. Metal deposits form at appropriate conductive interconnects
Is done. Load Impedance Device Intrinsic-Extrinsic Contact
Direct undoped intrinsic semiconductor region 22 to power supply node 42
By making electrical connections, the gate interconnects
The polysilicon layer 20 is electrically connected to the common power supply node.
Continued. Impedance device R₁ , R_Two Alternative embodiment of
Then, the gate mutual composed of the first and second diffusion extrinsic regions
The connecting portions 24 and 43 are the intermediate undoped intrinsic semiconductor region 22.
Formed by diffusion in the interconnections on both sides of the
Have been. In that embodiment, the gate connection
Common polycrystalline silicon layer 20) and common power supply node (that is,
The electrical coupling with the metal adherend 42) is the second diffusion extrinsic
The region 43 is electrically connected directly to the common power node,
Diffusion extrinsic region 24 to the drain node of the transistor
By electrically connecting to. The process steps for impurity diffusion are conventional techniques.
For example, the surface of the substrate is brought to a temperature around 1,100 ° C.
Necessary impurities, for example, in the case of a P-channel device,
Exposure to gas containing phosphorus or N-channel devices
It is done by The mask 44 is an impurity such as boron and phosphorus.
Silicon nitride provides an effective mask for the diffusion of substances
Is formed. Silicon nitride is silane and ammonia
400 ° C to 1,100 ° C with excess hydrogen
In the temperature range of
It is deposited on the connection area 20. After this diffusion stage,
A 1,000 mm oxide layer was deposited over the top area
The oxide layer also has a V_DDNo
The forging applied to form the metal deposit
Masked by photoresist. Each transistor Q₁ And Q_Two Game
G interconnects 24 and 43 are bonded to the drain power node.
Data node 1 is Q₁ Conductive mutual in the drain region of
Integrated circuit is formed by connecting with connecting material (not shown)
Is done. Q₁ Drain region and Q_Two Gate interconnect
By forming a conductive interconnect with 24
Data node 1. Similarly, Q_Two Dray of
Area and Q₁ Conductive between corresponding gate interconnects of
Data node 2 is configured by forming a sex interconnect.
Is done. Ultra-low current load device R₁ , R_Two DC imp
Can reduce the amount of exogenous impurities in these devices.
Through the undoped intrinsic semiconductor region 22
Diffuses until it is transformed into a lightly doped extrinsic region
Can be reduced somewhat. This and
The intrinsic-exogenous junction 28 is transformed into an extrinsic-exogenous junction 48.
The latter, but the latter has a high impurity concentration and a relatively low impurity concentration.
That the impurity regions are
Features. In that case, both impurity concentrations are the same conductivity type.
Or the reverse conductivity type. However, extremely high DC
In order to realize the impedance, the impurity concentration
It is essentially important that the bells are substantially
is there. The ion implantation step described here is a conventional step.
On implantation techniques, for example, US Pat. No. 3,898,105.
This is accomplished by the technique disclosed in US Pat. Either logical "1" or logical "0"
5V at data nodes 1 and 2 corresponding to
40m in standby mode within the operating range of 2.5V
Considering the design load of W, 4K bits (409
In a 6-bit memory, each bit is the power consumption of a memory cell.
It consumes 0.01 mW of power as the maximum allowable cost.
At 5V, the impedance load device R₁, R_TwoBy 1 negative
If a current of 2 μA or less must be supplied per loading device
Absent. Therefore, the low-load device R₁And R_TwoImpedance of
The lower limit of the range, that is, 2.5 MΩ as the minimum resistance value
There is a value. Transistor Q₁And Q_TwoExpected maximum of
The upper limit of the impedance range corresponding to leakage, that is, the maximum
Resistance value is 2.5V 10nA (Q₁And Q_TwoAgainst
Maximum leakage current) divided by 250 MΩ
It turns out that it becomes. Of the undoped polycrystalline silicon region 22
N-type extrinsic doping of purity and polycrystalline silicon layer 20
Within a certain temperature range by carefully controlling the
To realize a memory cell that consumes the least amount of current.
R₁And R_TwoThe resistance value of the
From the condition of maximum expected leakage current value at elevated operating temperature
R₁And R_TwoControl the resistance value of 2.5 to 250 MΩ.
You can control.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 RA using a memory cell of an application example of the present invention
FIG. FIG. 2 is an electric circuit diagram of the memory cell of FIG. 1; FIG. 3 is a layout view of the circuit of FIG. 2 on a substrate. FIG. 4 is a sectional view taken along line IV-IV of FIG. 3; FIG. 5 is a cross-sectional view of a preferred embodiment of a gate interconnect having a load impedance device constructed in accordance with the present invention. FIG. 6 is a cross-sectional view of a gate interconnect according to another embodiment of a load impedance device. 7A and 7B are cross-sectional views of another embodiment of the load impedance device configured according to the present invention. 8A and 8B are cross-sectional views of still another embodiment of the load impedance device configured according to the present invention. 9A and 9B are cross-sectional views of still another embodiment of the load impedance device configured according to the present invention. 10A and 10B are cross-sectional views of still another embodiment of the load impedance device configured according to the present invention. [Description of Reference Signs] 1, Data Node 10 Memory Cell 20 Intrinsic Polycrystalline Silicon Semiconductor Layer 22 First Conduction Path 24 Second Conduction Path 28 Intrinsic-Extrinsic Junction V _DD Drain Power Supply Node V _ss Source Power Supply Node R Impedance Device Q Insulated gate field effect transistor D, D Complementary data bus RA row address line

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Tsui Chiu Chiyan               Carrollt, Texas, United States               Camaro Drive 1633                (56) References JP-A-50-11644 (JP, A)

Claims (1)

(57) [Claims] A drain power supply node, a source power supply node, first and second data input / output nodes which are complementary to each other, and insulated gate field effect type first and second transistors are provided. Each channel of the transistor can electrically connect the corresponding first and second data input / output nodes to the source power supply node, and the gate of the first transistor has the second data input / output. An integrated circuit binary memory cell electrically connected to a node and having a gate of the second transistor electrically connected to the first data input / output node. First and second impedance devices, each electrically connected to the drain power node, are provided, each impedance device being a conductive path. Defining a substrate of semiconductor material, the substrate having a substantially intrinsic region and a doped region doped with exogenous impurities, the boundary between the substantially intrinsic region and the doped region Defines an intrinsic-extrinsic junction, each impedance device forms a series electrical path between the drain power node and a corresponding data input / output node, and the maximum allowable power dissipation of the memory cell. The resistance value is set to a range between a minimum resistance value determined based on the value and a maximum resistance value determined based on the predicted maximum value of the leakage current of the memory cell. Integrated circuit binary memory cell.