JPS6145496A - デコ−ダ回路 - Google Patents
デコ−ダ回路Info
- Publication number
- JPS6145496A JPS6145496A JP59166114A JP16611484A JPS6145496A JP S6145496 A JPS6145496 A JP S6145496A JP 59166114 A JP59166114 A JP 59166114A JP 16611484 A JP16611484 A JP 16611484A JP S6145496 A JPS6145496 A JP S6145496A
- Authority
- JP
- Japan
- Prior art keywords
- nand gate
- output
- transistor
- inverter
- load
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Static Random-Access Memory (AREA)
- Read Only Memory (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59166114A JPS6145496A (ja) | 1984-08-08 | 1984-08-08 | デコ−ダ回路 |
| US06/759,980 US4782247A (en) | 1984-08-08 | 1985-07-29 | Decoder circuit having a variable power supply |
| EP85109709A EP0171718B1 (en) | 1984-08-08 | 1985-08-02 | Decoder circuit in an ic memory chip |
| KR1019850005581A KR900002910B1 (ko) | 1984-08-08 | 1985-08-02 | Ic메모리 칩내의 디코더회로 |
| DE8585109709T DE3585573D1 (de) | 1984-08-08 | 1985-08-02 | Dekodierschaltung in einem integrierten speicherchip. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59166114A JPS6145496A (ja) | 1984-08-08 | 1984-08-08 | デコ−ダ回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6145496A true JPS6145496A (ja) | 1986-03-05 |
| JPH0546639B2 JPH0546639B2 (enrdf_load_stackoverflow) | 1993-07-14 |
Family
ID=15825281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59166114A Granted JPS6145496A (ja) | 1984-08-08 | 1984-08-08 | デコ−ダ回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6145496A (enrdf_load_stackoverflow) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02108293A (ja) * | 1988-10-15 | 1990-04-20 | Sony Corp | 不揮発性メモリのアドレスデコーダ回路 |
| JPH02114717A (ja) * | 1988-10-25 | 1990-04-26 | Fujitsu Ltd | 半導体記憶装置 |
| US5038327A (en) * | 1989-09-20 | 1991-08-06 | Fujitsu Limited | Decoder circuit of erasable programmable read only memory for avoiding erroneous operation caused by parasitic capacitors |
| JP2014142989A (ja) * | 2013-01-22 | 2014-08-07 | Freescale Semiconductor Inc | ワード線/行ドライバのためのバイアス電圧を用いるフラッシュメモリ |
| EP2092204B2 (de) † | 2006-11-16 | 2022-10-26 | thyssenkrupp rothe erde Germany GmbH | Wälzlager, insbesondere mittenfreies grosswälzlager |
-
1984
- 1984-08-08 JP JP59166114A patent/JPS6145496A/ja active Granted
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02108293A (ja) * | 1988-10-15 | 1990-04-20 | Sony Corp | 不揮発性メモリのアドレスデコーダ回路 |
| JPH02114717A (ja) * | 1988-10-25 | 1990-04-26 | Fujitsu Ltd | 半導体記憶装置 |
| US5018107A (en) * | 1988-10-25 | 1991-05-21 | Fujitsu Limited | Semiconductor memory device |
| US5038327A (en) * | 1989-09-20 | 1991-08-06 | Fujitsu Limited | Decoder circuit of erasable programmable read only memory for avoiding erroneous operation caused by parasitic capacitors |
| EP2092204B2 (de) † | 2006-11-16 | 2022-10-26 | thyssenkrupp rothe erde Germany GmbH | Wälzlager, insbesondere mittenfreies grosswälzlager |
| JP2014142989A (ja) * | 2013-01-22 | 2014-08-07 | Freescale Semiconductor Inc | ワード線/行ドライバのためのバイアス電圧を用いるフラッシュメモリ |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0546639B2 (enrdf_load_stackoverflow) | 1993-07-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR0155078B1 (ko) | 강전계용의 mos 회로를 갖춘 반도체 회로 | |
| KR900002910B1 (ko) | Ic메모리 칩내의 디코더회로 | |
| JPH06119784A (ja) | センスアンプとそれを用いたsramとマイクロプロセッサ | |
| KR0179553B1 (ko) | 로오 디코더 및 컬럼 디코더 회로 | |
| JP2994120B2 (ja) | 半導体記憶装置 | |
| JPH05101686A (ja) | マイクロコンピユータ | |
| CN110176924B (zh) | 半导体器件 | |
| JPS6145496A (ja) | デコ−ダ回路 | |
| JP2003157688A (ja) | 電圧トランスレータ | |
| KR100385463B1 (ko) | 반도체 메모리 장치의 워드라인 제어회로 | |
| JPH0437217A (ja) | 論理レベル変換回路 | |
| JPH09245482A (ja) | 論理回路及び半導体記憶装置 | |
| JPS6260759B2 (enrdf_load_stackoverflow) | ||
| JP2504410B2 (ja) | 半導体記憶装置 | |
| KR100254473B1 (ko) | 로오 디코더 회로 | |
| JP3192106B2 (ja) | 半導体集積回路 | |
| JPS6325438B2 (enrdf_load_stackoverflow) | ||
| JPH0311127B2 (enrdf_load_stackoverflow) | ||
| KR100233271B1 (ko) | 디코더 회로에서 전력 소비 감소 방법 | |
| JPS6043586B2 (ja) | アドレスデコ−ダ回路 | |
| KR100265590B1 (ko) | 반도체 메모리 소자의 로오 디코더 장치 | |
| JPH0738001B2 (ja) | 電位検知回路 | |
| KR100378336B1 (ko) | 반도체장치의기억회로 | |
| KR100314646B1 (ko) | 부트스트랩회로 | |
| JPH0737385A (ja) | 内部電源用降圧回路 |