DE3585573D1 - Dekodierschaltung in einem integrierten speicherchip. - Google Patents

Dekodierschaltung in einem integrierten speicherchip.

Info

Publication number
DE3585573D1
DE3585573D1 DE8585109709T DE3585573T DE3585573D1 DE 3585573 D1 DE3585573 D1 DE 3585573D1 DE 8585109709 T DE8585109709 T DE 8585109709T DE 3585573 T DE3585573 T DE 3585573T DE 3585573 D1 DE3585573 D1 DE 3585573D1
Authority
DE
Germany
Prior art keywords
memory chip
decoder circuit
integrated memory
integrated
decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585109709T
Other languages
English (en)
Inventor
Masanobu Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59166114A external-priority patent/JPS6145496A/ja
Priority claimed from JP59182417A external-priority patent/JPS6161295A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3585573D1 publication Critical patent/DE3585573D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
DE8585109709T 1984-08-08 1985-08-02 Dekodierschaltung in einem integrierten speicherchip. Expired - Fee Related DE3585573D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59166114A JPS6145496A (ja) 1984-08-08 1984-08-08 デコ−ダ回路
JP59182417A JPS6161295A (ja) 1984-08-31 1984-08-31 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3585573D1 true DE3585573D1 (de) 1992-04-16

Family

ID=26490607

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585109709T Expired - Fee Related DE3585573D1 (de) 1984-08-08 1985-08-02 Dekodierschaltung in einem integrierten speicherchip.

Country Status (4)

Country Link
US (1) US4782247A (de)
EP (1) EP0171718B1 (de)
KR (1) KR900002910B1 (de)
DE (1) DE3585573D1 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2219901B (en) * 1988-06-17 1992-10-07 Motorola Inc Eprom programming
US4875191A (en) * 1988-07-21 1989-10-17 Intel Corporation Integrated read and programming row driver
JPH0821849B2 (ja) * 1988-10-25 1996-03-04 富士通株式会社 半導体記憶装置
JPH0793022B2 (ja) * 1988-12-24 1995-10-09 株式会社東芝 半導体メモリ集積回路
JPH0334198A (ja) * 1989-06-30 1991-02-14 Fujitsu Ltd 書き換え可能な不揮発性メモリ
JP2606941B2 (ja) * 1990-02-19 1997-05-07 富士通株式会社 不揮発性メモリの書込み回路
US5058065A (en) * 1990-02-26 1991-10-15 Eastman Kodak Company Memory based line-delay architecture
US5142494A (en) * 1990-02-26 1992-08-25 Eastman Kodak Company Memory based line-delay architecture
GB9007790D0 (en) 1990-04-06 1990-06-06 Lines Valerie L Dynamic memory wordline driver scheme
JPH04225182A (ja) 1990-12-26 1992-08-14 Toshiba Corp 半導体記憶装置
US5506803A (en) * 1992-04-01 1996-04-09 Intel Corporation Apparatus and method for minimizing verify time in a semiconductor memory by constantly charging n-well capacitance
US5675824A (en) * 1992-09-30 1997-10-07 Intel Corporation Programmable logic having selectable output voltages
KR960006373B1 (ko) * 1992-10-31 1996-05-15 삼성전자주식회사 반도체 메모리 장치의 워드라인 구동회로
JP3267436B2 (ja) * 1993-04-19 2002-03-18 三菱電機株式会社 半導体装置
US5696464A (en) * 1993-10-22 1997-12-09 At&T Global Information Solutions Company Output driver adaptable to power supply variation
KR0124046B1 (ko) * 1993-11-18 1997-11-25 김광호 반도체메모리장치의 승압레벨 감지회로
US5798885A (en) * 1994-06-06 1998-08-25 Fujitsu Limited Head positioning control for disk apparatus using peak detection, polarity detection and sector mark detection
US5796673A (en) 1994-10-06 1998-08-18 Mosaid Technologies Incorporated Delay locked loop implementation in a synchronous dynamic random access memory
US8782477B2 (en) * 2011-05-11 2014-07-15 Jabil Circuit, Inc. High-speed serial interface bridge adapter for signal integrity verification
US8913436B2 (en) * 2013-03-14 2014-12-16 Freescale Semiconductor, Inc. Non-volatile memory (NVM) with word line driver/decoder using a charge pump voltage

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1375958A (en) * 1972-06-29 1974-12-04 Ibm Pulse circuit
US3982138A (en) * 1974-10-09 1976-09-21 Rockwell International Corporation High speed-low cost, clock controlled CMOS logic implementation
JPS5833638B2 (ja) * 1979-09-21 1983-07-21 株式会社日立製作所 メモリ装置
JPS5673542A (en) * 1979-11-22 1981-06-18 Kureha Chem Ind Co Ltd Adsorbent
JPS5831677B2 (ja) * 1979-11-26 1983-07-07 富士通株式会社 半導体記億装置
GB2094086B (en) * 1981-03-03 1985-08-14 Tokyo Shibaura Electric Co Non-volatile semiconductor memory system
JPS57147196A (en) * 1981-03-06 1982-09-10 Fujitsu Ltd Read-only memory
US4415993A (en) * 1981-11-23 1983-11-15 The United States Of America As Represented By The Secretary Of The Air Force Fast access non-volatile memory
US4514829A (en) * 1982-12-30 1985-04-30 International Business Machines Corporation Word line decoder and driver circuits for high density semiconductor memory

Also Published As

Publication number Publication date
KR900002910B1 (ko) 1990-05-03
US4782247A (en) 1988-11-01
KR860002150A (ko) 1986-03-26
EP0171718A3 (en) 1987-12-02
EP0171718B1 (de) 1992-03-11
EP0171718A2 (de) 1986-02-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee