JPS59150444A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS59150444A
JPS59150444A JP58015952A JP1595283A JPS59150444A JP S59150444 A JPS59150444 A JP S59150444A JP 58015952 A JP58015952 A JP 58015952A JP 1595283 A JP1595283 A JP 1595283A JP S59150444 A JPS59150444 A JP S59150444A
Authority
JP
Japan
Prior art keywords
film
polycrystalline silicon
nitride film
region
element region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58015952A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6337502B2 (enExample
Inventor
Yoshitaka Hasegawa
長谷川　義隆
Toshihiko Minamida
南田　敏彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58015952A priority Critical patent/JPS59150444A/ja
Publication of JPS59150444A publication Critical patent/JPS59150444A/ja
Publication of JPS6337502B2 publication Critical patent/JPS6337502B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
JP58015952A 1983-02-02 1983-02-02 半導体装置の製造方法 Granted JPS59150444A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58015952A JPS59150444A (ja) 1983-02-02 1983-02-02 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58015952A JPS59150444A (ja) 1983-02-02 1983-02-02 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS59150444A true JPS59150444A (ja) 1984-08-28
JPS6337502B2 JPS6337502B2 (enExample) 1988-07-26

Family

ID=11903082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58015952A Granted JPS59150444A (ja) 1983-02-02 1983-02-02 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS59150444A (enExample)

Also Published As

Publication number Publication date
JPS6337502B2 (enExample) 1988-07-26

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