JPS6337502B2 - - Google Patents

Info

Publication number
JPS6337502B2
JPS6337502B2 JP58015952A JP1595283A JPS6337502B2 JP S6337502 B2 JPS6337502 B2 JP S6337502B2 JP 58015952 A JP58015952 A JP 58015952A JP 1595283 A JP1595283 A JP 1595283A JP S6337502 B2 JPS6337502 B2 JP S6337502B2
Authority
JP
Japan
Prior art keywords
film
nitride film
polycrystalline silicon
element region
silicon film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58015952A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59150444A (ja
Inventor
Yoshitaka Hasegawa
Toshihiko Minamida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP58015952A priority Critical patent/JPS59150444A/ja
Publication of JPS59150444A publication Critical patent/JPS59150444A/ja
Publication of JPS6337502B2 publication Critical patent/JPS6337502B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/011Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/13Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
JP58015952A 1983-02-02 1983-02-02 半導体装置の製造方法 Granted JPS59150444A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58015952A JPS59150444A (ja) 1983-02-02 1983-02-02 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58015952A JPS59150444A (ja) 1983-02-02 1983-02-02 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS59150444A JPS59150444A (ja) 1984-08-28
JPS6337502B2 true JPS6337502B2 (enExample) 1988-07-26

Family

ID=11903082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58015952A Granted JPS59150444A (ja) 1983-02-02 1983-02-02 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS59150444A (enExample)

Also Published As

Publication number Publication date
JPS59150444A (ja) 1984-08-28

Similar Documents

Publication Publication Date Title
JPS6340337A (ja) 集積回路分離法
JPH0529133B2 (enExample)
JPS618945A (ja) 半導体集積回路装置
JPS60147133A (ja) 半導体基板内に溝を形成する方法
US4657630A (en) Method for manufacturing semiconductor device having isolating groove
JPH0216574B2 (enExample)
JPS63107119A (ja) ステップ絶縁層を有する集積回路の製造方法
JP3178416B2 (ja) 半導体装置の製造方法
JPS59165434A (ja) 半導体装置の製造方法
EP0120614B1 (en) Method of manufacturing a semiconductor device having isolation regions
JPH11260903A (ja) 無空洞トレンチ隔離を形成する方法
JPS6337502B2 (enExample)
US6245643B1 (en) Method of removing polysilicon residual in a LOCOS isolation process using an etching selectivity solution
JPH04150030A (ja) 半導体装置の製造方法
KR940009578B1 (ko) 반도체 장치 및 그 제조방법
JPS6231492B2 (enExample)
JPH05304143A (ja) 素子分離領域の形成方法
JPH05206263A (ja) 半導体装置の製造方法
KR930008845B1 (ko) 반도체소자의 소자 격리방법
JPS62112342A (ja) 素子分離領域の形成方法
JPH08203882A (ja) 半導体装置の製造方法
JPH1050695A (ja) 半導体装置の製造方法
JPH0458538A (ja) 半導体装置の製造方法
JPH05190485A (ja) 半導体装置の製造方法
JPS5994842A (ja) 半導体装置の製造方法