JPH1174527A5 - - Google Patents

Info

Publication number
JPH1174527A5
JPH1174527A5 JP1998185452A JP18545298A JPH1174527A5 JP H1174527 A5 JPH1174527 A5 JP H1174527A5 JP 1998185452 A JP1998185452 A JP 1998185452A JP 18545298 A JP18545298 A JP 18545298A JP H1174527 A5 JPH1174527 A5 JP H1174527A5
Authority
JP
Japan
Prior art keywords
insulating film
forming
film
gate
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1998185452A
Other languages
English (en)
Japanese (ja)
Other versions
JPH1174527A (ja
JP4160167B2 (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP18545298A priority Critical patent/JP4160167B2/ja
Priority claimed from JP18545298A external-priority patent/JP4160167B2/ja
Publication of JPH1174527A publication Critical patent/JPH1174527A/ja
Publication of JPH1174527A5 publication Critical patent/JPH1174527A5/ja
Application granted granted Critical
Publication of JP4160167B2 publication Critical patent/JP4160167B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP18545298A 1997-06-30 1998-06-30 半導体装置の製造方法 Expired - Fee Related JP4160167B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18545298A JP4160167B2 (ja) 1997-06-30 1998-06-30 半導体装置の製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP9-174552 1997-06-30
JP17455297 1997-06-30
JP18545298A JP4160167B2 (ja) 1997-06-30 1998-06-30 半導体装置の製造方法

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2008024576A Division JP2008153686A (ja) 1997-06-30 2008-02-04 半導体装置の製造方法
JP2008024577A Division JP2008153687A (ja) 1997-06-30 2008-02-04 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JPH1174527A JPH1174527A (ja) 1999-03-16
JPH1174527A5 true JPH1174527A5 (enrdf_load_html_response) 2005-05-26
JP4160167B2 JP4160167B2 (ja) 2008-10-01

Family

ID=26496128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18545298A Expired - Fee Related JP4160167B2 (ja) 1997-06-30 1998-06-30 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP4160167B2 (enrdf_load_html_response)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4564467B2 (ja) * 1998-06-29 2010-10-20 株式会社東芝 Ｍｉｓ型トランジスタおよびその製造方法
JP3600476B2 (ja) 1999-06-30 2004-12-15 株式会社東芝 半導体装置の製造方法
JP4491858B2 (ja) * 1999-07-06 2010-06-30 ソニー株式会社 半導体装置の製造方法
JP3773448B2 (ja) * 2001-06-21 2006-05-10 松下電器産業株式会社 半導体装置
US6624043B2 (en) * 2001-09-24 2003-09-23 Sharp Laboratories Of America, Inc. Metal gate CMOS and method of manufacturing the same
US6713335B2 (en) * 2002-08-22 2004-03-30 Chartered Semiconductor Manufacturing Ltd. Method of self-aligning a damascene gate structure to isolation regions
KR100499159B1 (ko) * 2003-02-28 2005-07-01 삼성전자주식회사 리세스 채널을 갖는 반도체장치 및 그 제조방법
KR100539265B1 (ko) 2004-05-28 2005-12-27 삼성전자주식회사 리세스 채널 ｍｏｓｆｅｔ 제조방법
JP4552603B2 (ja) * 2004-11-08 2010-09-29 エルピーダメモリ株式会社 半導体装置の製造方法
US8338887B2 (en) 2005-07-06 2012-12-25 Infineon Technologies Ag Buried gate transistor
US8652912B2 (en) 2006-12-08 2014-02-18 Micron Technology, Inc. Methods of fabricating a transistor gate including cobalt silicide
JP2008171872A (ja) * 2007-01-09 2008-07-24 Elpida Memory Inc 半導体装置及びその製造方法
JP5487625B2 (ja) * 2009-01-22 2014-05-07 ソニー株式会社 半導体装置
US8436404B2 (en) 2009-12-30 2013-05-07 Intel Corporation Self-aligned contacts
JP5223907B2 (ja) * 2010-11-01 2013-06-26 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
JP2014241386A (ja) * 2013-06-12 2014-12-25 富士通セミコンダクター株式会社 半導体装置の製造方法及び半導体装置
JP7045974B2 (ja) * 2018-11-14 2022-04-01 東京エレクトロン株式会社 デバイスの製造方法

Similar Documents

Publication Publication Date Title
TWI390666B (zh) 絕緣體上半導體裝置之製造方法
US6476444B1 (en) Semiconductor device and method for fabricating the same
CN100466208C (zh) 随机存取存储器及其制造方法
TWI389200B (zh) 形成層間介電質之方法
JPH1174527A5 (enrdf_load_html_response)
KR970004045A (ko) 소이(soi) 구조의 모스 트랜지스터 및 그 제조방법
US8586426B2 (en) Method of forming isolation structures for SOI devices with ultrathin SOI and ultrathin box
JPH10189966A5 (enrdf_load_html_response)
US7705401B2 (en) Semiconductor device including a fin-channel recess-gate MISFET
US20150162438A1 (en) Memory device employing an inverted u-shaped floating gate
KR910013554A (ko) 반도체 장치 및 그 제조방법
TWI226667B (en) Transistor fabrication method
US20030042568A1 (en) Method of manufacturing MOSEFT and structure thereof
JP4122181B2 (ja) 二重ゲート酸化膜を有する半導体素子の製造方法
JPH1174526A5 (enrdf_load_html_response)
CN115621314A (zh) 半导体结构及其形成方法
CN113224157B (zh) 半导体结构及其形成方法
KR100477786B1 (ko) 반도체소자의 콘택 형성 방법
KR100344837B1 (ko) 반도체 소자 및 그의 제조방법
KR100368971B1 (ko) 에스오아이 소자의 게이트 및 그 제조방법
KR20040049121A (ko) 디램 장치 트랜지스터의 게이트 스페이서 형성 방법
KR20060046879A (ko) 멀티-브리지 채널형 모오스 트랜지스터의 제조 방법
KR920003557A (ko) 반도체 장치 및 그 방법
KR100290912B1 (ko) 반도체소자의 격리막 형성방법
KR100370144B1 (ko) 반도체 소자의 이중게이트 형성 방법