KR970004045A - 소이(soi) 구조의 모스 트랜지스터 및 그 제조방법 - Google Patents

소이(soi) 구조의 모스 트랜지스터 및 그 제조방법 Download PDF

Info

Publication number
KR970004045A
KR970004045A KR1019950015594A KR19950015594A KR970004045A KR 970004045 A KR970004045 A KR 970004045A KR 1019950015594 A KR1019950015594 A KR 1019950015594A KR 19950015594 A KR19950015594 A KR 19950015594A KR 970004045 A KR970004045 A KR 970004045A
Authority
KR
South Korea
Prior art keywords
depth
semiconductor substrate
insulating film
source
mos transistor
Prior art date
Application number
KR1019950015594A
Other languages
English (en)
Other versions
KR100189966B1 (ko
Inventor
박규찬
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950015594A priority Critical patent/KR100189966B1/ko
Priority to JP11788696A priority patent/JP3489936B2/ja
Priority to US08/664,958 priority patent/US5893745A/en
Publication of KR970004045A publication Critical patent/KR970004045A/ko
Priority to US09/291,416 priority patent/US6064092A/en
Application granted granted Critical
Publication of KR100189966B1 publication Critical patent/KR100189966B1/ko
Priority to US09/541,201 priority patent/US6303412B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76275—Vertical isolation by bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

소이(SOI) 구조의 모스 트랜지스터 및 그 제조방법에 대해 기재한다.
이는, 반도체 기판, 반도체 기판 상에 형성된 절연막, 절연막 내에 위치하고, 소오스/드레인영역은 절연막의 표면으로부터 제1의 깊이를 가지며, 채널영역은 제1의 깊이보다 얕은 제2의 깊이를 가지는 실리콘층, 실리콘층상에 형성된 게이트절연막 및 게이트절연막 상에 형성된 게이트전극을 포함하는 것을 특징으로 한다.
따라서, 전극과 소오스/드레인의 접촉저항을 낮출 수 있으며, 소오스/드레인의 면저항을 줄일 수 있다.

Description

소이(SOI) 구조의 모스 트랜지스터 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 일 실시예에 의해 제조된 SOI 구조의 모스 트랜지스터를 도시한 단면도이다.

Claims (6)

  1. 반도체 기판; 상기 반도체 기판 상에 형성된 절연막; 상기 절연막 내에 위치하고, 소오스/드레인영역은 상기 절연막의 표면으로부터 제1의 깊이를 가지며, 채널영역은 상기 제1의 깊이보다 얕은 제2의 깊이를 가지는 실리콘층; 및 상기 실리콘층 상에 게이트절연막을 개재하여 형성된 게이트전극을 구비하는 것을 특징으로 하는 소이 구조의 모스 트랜지스터.
  2. 제1항에 있어서, 상기 게이트전극이 소오스/드레인을 오버랩하는 것을 특징으로 하는 소이 구조의 모스 트랜지스터.
  3. 제1항에 있어서, 상기 제1의 깊이는 1,000~3,000Å이고, 상기 제2의 깊이는 1,000Å 이하인 것을 특징으로 하는 소이 모스 트랜지스터
  4. 반도체 기판 상에 소오스/드레인이 형성될 영역을 노출시키지 않는 질화막패턴을 형성하는 제1공정; 결과물 상에 산화물을 침적한 후 에치백하여, 상기 질화막패턴 사이를 채우며, 상기 질화막패턴의 측벽에 스페이서를 형성하는 제2공정; 상기 반도체 기판을 산화시켜 필드산화막을 형성하는 제3공정; 상기 질화막패턴을 제거하는 제4공정; 결과물 전면에 산화물을 침적한 후, 그 표면을 평탄화하는 제5공정; 상기 반도체 기판에 핸들링 기판을 본딩하는 제6공정; 및 상기 반도체 기판을 폴리슁하는 제7공정을 포함하는 것을 특징으로 하는 소이 구조의 모스 트랜지스터 제조방법.
  5. 제4항에 있어서, 산화물의 표면을 평탄화하는 상기 제5공정 및 상기 제7공정은 화학적-물리적 연마(CMP)법을 사용하여 이루어지는 것을 특징으로 하는 소이 구조의 모스 트랜지스터 제조방법.
  6. 제4항에 있어서, 상기 제7공정은 비활성영역에 형성된 필드산화막을 식각종말점으로 하여 진행되는 것을 특징으로 하는 소이 구조의 모스 트랜지스터 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950015594A 1995-06-13 1995-06-13 소이 구조의 모스 트랜지스터 및 그 제조방법 KR100189966B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019950015594A KR100189966B1 (ko) 1995-06-13 1995-06-13 소이 구조의 모스 트랜지스터 및 그 제조방법
JP11788696A JP3489936B2 (ja) 1995-06-13 1996-05-13 Ｓｏｉ構造のｍｏｓトランジスタの製造方法
US08/664,958 US5893745A (en) 1995-06-13 1996-06-13 Methods of forming semiconductor-on-insulator substrates
US09/291,416 US6064092A (en) 1995-06-13 1999-04-13 Semiconductor-on-insulator substrates containing electrically insulating mesas
US09/541,201 US6303412B1 (en) 1995-06-13 2000-04-03 Methods of forming semiconductor-on-insulator substrates and devices and structures formed thereby

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950015594A KR100189966B1 (ko) 1995-06-13 1995-06-13 소이 구조의 모스 트랜지스터 및 그 제조방법

Publications (2)

Publication Number Publication Date
KR970004045A true KR970004045A (ko) 1997-01-29
KR100189966B1 KR100189966B1 (ko) 1999-06-01

Family

ID=19417013

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950015594A KR100189966B1 (ko) 1995-06-13 1995-06-13 소이 구조의 모스 트랜지스터 및 그 제조방법

Country Status (3)

Country Link
US (3) US5893745A (ko)
JP (1) JP3489936B2 (ko)
KR (1) KR100189966B1 (ko)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100189966B1 (ko) * 1995-06-13 1999-06-01 윤종용 소이 구조의 모스 트랜지스터 및 그 제조방법
US6194253B1 (en) * 1998-10-07 2001-02-27 International Business Machines Corporation Method for fabrication of silicon on insulator substrates
US6693033B2 (en) 2000-02-10 2004-02-17 Motorola, Inc. Method of removing an amorphous oxide from a monocrystalline surface
US6392257B1 (en) 2000-02-10 2002-05-21 Motorola Inc. Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
US6477285B1 (en) 2000-06-30 2002-11-05 Motorola, Inc. Integrated circuits with optical signal propagation
US6410941B1 (en) 2000-06-30 2002-06-25 Motorola, Inc. Reconfigurable systems using hybrid integrated circuits with optical ports
US6501973B1 (en) 2000-06-30 2002-12-31 Motorola, Inc. Apparatus and method for measuring selected physical condition of an animate subject
US6427066B1 (en) 2000-06-30 2002-07-30 Motorola, Inc. Apparatus and method for effecting communications among a plurality of remote stations
US6555946B1 (en) 2000-07-24 2003-04-29 Motorola, Inc. Acoustic wave device and process for forming the same
US6437404B1 (en) * 2000-08-10 2002-08-20 Advanced Micro Devices, Inc. Semiconductor-on-insulator transistor with recessed source and drain
US6638838B1 (en) 2000-10-02 2003-10-28 Motorola, Inc. Semiconductor structure including a partially annealed layer and method of forming the same
US6583034B2 (en) 2000-11-22 2003-06-24 Motorola, Inc. Semiconductor structure including a compliant substrate having a graded monocrystalline layer and methods for fabricating the structure and semiconductor devices including the structure
US6563118B2 (en) 2000-12-08 2003-05-13 Motorola, Inc. Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same
US6657261B2 (en) * 2001-01-09 2003-12-02 International Business Machines Corporation Ground-plane device with back oxide topography
US6673646B2 (en) 2001-02-28 2004-01-06 Motorola, Inc. Growth of compound semiconductor structures on patterned oxide films and process for fabricating same
US6365445B1 (en) * 2001-05-01 2002-04-02 Advanced Micro Devices, Inc. Field effect transistor formed in SOI technology with semiconductor material having multiple thicknesses
US6624486B2 (en) * 2001-05-23 2003-09-23 International Business Machines Corporation Method for low topography semiconductor device formation
US6525340B2 (en) 2001-06-04 2003-02-25 International Business Machines Corporation Semiconductor device with junction isolation
US6709989B2 (en) 2001-06-21 2004-03-23 Motorola, Inc. Method for fabricating a semiconductor structure including a metal oxide interface with silicon
US6646293B2 (en) 2001-07-18 2003-11-11 Motorola, Inc. Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates
US6693298B2 (en) 2001-07-20 2004-02-17 Motorola, Inc. Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same
US6472694B1 (en) 2001-07-23 2002-10-29 Motorola, Inc. Microprocessor structure having a compound semiconductor layer
US6585424B2 (en) 2001-07-25 2003-07-01 Motorola, Inc. Structure and method for fabricating an electro-rheological lens
US6667196B2 (en) 2001-07-25 2003-12-23 Motorola, Inc. Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method
US6594414B2 (en) 2001-07-25 2003-07-15 Motorola, Inc. Structure and method of fabrication for an optical switch
US6639249B2 (en) 2001-08-06 2003-10-28 Motorola, Inc. Structure and method for fabrication for a solid-state lighting device
US6462360B1 (en) 2001-08-06 2002-10-08 Motorola, Inc. Integrated gallium arsenide communications systems
US6589856B2 (en) 2001-08-06 2003-07-08 Motorola, Inc. Method and apparatus for controlling anti-phase domains in semiconductor structures and devices
US6673667B2 (en) 2001-08-15 2004-01-06 Motorola, Inc. Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials
JP2003168802A (ja) * 2001-11-30 2003-06-13 Toshiba Corp 半導体装置及びその製造方法
JP3825688B2 (ja) * 2001-12-25 2006-09-27 株式会社東芝 半導体装置の製造方法
US6489193B1 (en) * 2002-01-09 2002-12-03 Silicon Integrated Systems Corp. Process for device isolation
US7075150B2 (en) * 2003-12-02 2006-07-11 International Business Machines Corporation Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique
US7247569B2 (en) * 2003-12-02 2007-07-24 International Business Machines Corporation Ultra-thin Si MOSFET device structure and method of manufacture
US7202123B1 (en) 2004-07-02 2007-04-10 Advanced Micro Devices, Inc. Mesa isolation technology for extremely thin silicon-on-insulator semiconductor devices
JP5113999B2 (ja) * 2004-09-28 2013-01-09 シャープ株式会社 水素イオン注入剥離方法
JP2014212191A (ja) 2013-04-18 2014-11-13 セイコーエプソン株式会社 半導体装置、電気光学装置、半導体装置の製造方法、電気光学装置の製造方法、及び電子機器

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58115832A (ja) * 1981-12-28 1983-07-09 Fujitsu Ltd 半導体装置の製造方法
JPH04226079A (ja) * 1990-04-17 1992-08-14 Canon Inc 半導体装置及びその製造方法及びそれを有する電子回路装置
US5436173A (en) * 1993-01-04 1995-07-25 Texas Instruments Incorporated Method for forming a semiconductor on insulator device
US5438173A (en) * 1994-01-27 1995-08-01 G & H Technology, Inc. Cell bypass switch
US5496764A (en) * 1994-07-05 1996-03-05 Motorola, Inc. Process for forming a semiconductor region adjacent to an insulating layer
KR100189966B1 (ko) * 1995-06-13 1999-06-01 윤종용 소이 구조의 모스 트랜지스터 및 그 제조방법

Also Published As

Publication number Publication date
JP3489936B2 (ja) 2004-01-26
US5893745A (en) 1999-04-13
US6064092A (en) 2000-05-16
JPH098320A (ja) 1997-01-10
KR100189966B1 (ko) 1999-06-01
US6303412B1 (en) 2001-10-16

Similar Documents

Publication Publication Date Title
KR970004045A (ko) 소이(soi) 구조의 모스 트랜지스터 및 그 제조방법
US7061055B2 (en) Double-gate field-effect transistor, integrated circuit using the transistor and method of manufacturing the same
TW334590B (en) Semiconductor device and its manufacture
KR970077642A (ko) 반도체 소자의 캐패시터 제조 방법
KR950010053A (ko) 메모리 셀의 비트 라인 비아 홀 제조방법
WO2004023533A3 (en) Semiconductor component and method of manufacture
KR100871976B1 (ko) 반도체 소자 및 그 제조 방법
KR100374227B1 (ko) 반도체소자의 제조방법
KR20010004237A (ko) 자기정렬 콘택 공정을 포함하는 반도체 메모리 소자 제조방법
TW200516713A (en) Method fabricating a memory device having a self-aligned contact
KR970054431A (ko) 모스 트랜지스터 및 그 제조방법
KR980006066A (ko) 반도체 장치의 소자 분리막 형성방법
KR930022481A (ko) 다결정 실리콘 게이트를 평탄화하는 집적 회로 제조방법
KR960043091A (ko) 반도체장치의 제조방법
KR970054360A (ko) 반도체소자의 트랜지스터 형성방법
KR970004070A (ko) 리세스 된 게이트 전극을 갖는 반도체장치 및 그 제조방법
KR100290912B1 (ko) 반도체소자의 격리막 형성방법
KR100679833B1 (ko) 반도체 소자 및 그 제조 방법
KR100455730B1 (ko) 반도체소자의 이중 게이트절연막 형성방법
KR970003520A (ko) 미세 반도체 소자의 콘택홀 형성방법
KR970077223A (ko) 콘택홀을 가지는 반도체 장치 및 그의 형성 방법
KR970023997A (ko) 게이트전극을 함몰시킨 소자분리막 및 그 제조방법
KR970052014A (ko) 이중 스토퍼를 이용한 soi 웨이퍼 제조방법
KR970054267A (ko) 플레쉬 메모리 소자 및 그 제조방법
KR20060067372A (ko) 낮은 게이트 저항을 갖는 모스 트랜지스터 및 그 제조 방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
J201 Request for trial against refusal decision
B701 Decision to grant
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20130102

Year of fee payment: 15

FPAY Annual fee payment

Payment date: 20140103

Year of fee payment: 16

FPAY Annual fee payment

Payment date: 20141231

Year of fee payment: 17

EXPY Expiration of term