JPH11203866A5 - - Google Patents

Info

Publication number
JPH11203866A5
JPH11203866A5 JP1998006499A JP649998A JPH11203866A5 JP H11203866 A5 JPH11203866 A5 JP H11203866A5 JP 1998006499 A JP1998006499 A JP 1998006499A JP 649998 A JP649998 A JP 649998A JP H11203866 A5 JPH11203866 A5 JP H11203866A5
Authority
JP
Japan
Prior art keywords
mos transistor
channel mos
conduction terminal
gate electrode
receives
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1998006499A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11203866A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP10006499A priority Critical patent/JPH11203866A/ja
Priority claimed from JP10006499A external-priority patent/JPH11203866A/ja
Priority to US09/124,514 priority patent/US6031782A/en
Priority to TW087114166A priority patent/TW409461B/zh
Priority to CNB98119270XA priority patent/CN1169156C/zh
Priority to KR1019980037986A priority patent/KR100306859B1/ko
Publication of JPH11203866A publication Critical patent/JPH11203866A/ja
Publication of JPH11203866A5 publication Critical patent/JPH11203866A5/ja
Pending legal-status Critical Current

Links

JP10006499A 1998-01-16 1998-01-16 半導体記憶装置 Pending JPH11203866A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP10006499A JPH11203866A (ja) 1998-01-16 1998-01-16 半導体記憶装置
US09/124,514 US6031782A (en) 1998-01-16 1998-07-29 Semiconductor memory device provided with an interface circuit consuming a reduced amount of current consumption
TW087114166A TW409461B (en) 1998-01-16 1998-08-27 Semiconductor memory device
CNB98119270XA CN1169156C (zh) 1998-01-16 1998-09-15 具备能抑制消耗电流的接口电路的半导体存储器
KR1019980037986A KR100306859B1 (ko) 1998-01-16 1998-09-15 소비전류를억제하는인터페이스회로를구비하는반도체기억장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10006499A JPH11203866A (ja) 1998-01-16 1998-01-16 半導体記憶装置

Publications (2)

Publication Number Publication Date
JPH11203866A JPH11203866A (ja) 1999-07-30
JPH11203866A5 true JPH11203866A5 (enExample) 2005-08-04

Family

ID=11640149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10006499A Pending JPH11203866A (ja) 1998-01-16 1998-01-16 半導体記憶装置

Country Status (5)

Country Link
US (1) US6031782A (enExample)
JP (1) JPH11203866A (enExample)
KR (1) KR100306859B1 (enExample)
CN (1) CN1169156C (enExample)
TW (1) TW409461B (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6347379B1 (en) * 1998-09-25 2002-02-12 Intel Corporation Reducing power consumption of an electronic device
US6330635B1 (en) * 1999-04-16 2001-12-11 Intel Corporation Multiple user interfaces for an integrated flash device
TW522399B (en) * 1999-12-08 2003-03-01 Hitachi Ltd Semiconductor device
KR100443907B1 (ko) * 2001-09-07 2004-08-09 삼성전자주식회사 어드레스 버퍼 및 이를 이용한 반도체 메모리 장치
US6771553B2 (en) 2001-10-18 2004-08-03 Micron Technology, Inc. Low power auto-refresh circuit and method for dynamic random access memories
US6976181B2 (en) * 2001-12-20 2005-12-13 Intel Corporation Method and apparatus for enabling a low power mode for a processor
JP3667700B2 (ja) 2002-03-06 2005-07-06 エルピーダメモリ株式会社 入力バッファ回路及び半導体記憶装置
US6731548B2 (en) * 2002-06-07 2004-05-04 Micron Technology, Inc. Reduced power registered memory module and method
KR100506929B1 (ko) * 2002-08-08 2005-08-09 삼성전자주식회사 동기형 반도체 메모리 장치의 입력버퍼
KR100502664B1 (ko) 2003-04-29 2005-07-20 주식회사 하이닉스반도체 온 다이 터미네이션 모드 전환 회로 및 그방법
JP4592281B2 (ja) * 2003-12-18 2010-12-01 ルネサスエレクトロニクス株式会社 Ｌｓｉのインタフェース回路
KR100571651B1 (ko) * 2003-12-29 2006-04-17 주식회사 하이닉스반도체 파워다운 모드의 안정적인 탈출을 위한 제어회로
US7545194B2 (en) * 2006-06-30 2009-06-09 Intel Corporation Programmable delay for clock phase error correction
KR100914074B1 (ko) 2007-10-09 2009-08-28 창원대학교 산학협력단 고속 신호 전송과 저전력 소비를 구현하는 수신기
US7715264B2 (en) * 2008-06-24 2010-05-11 Qimonda North America Corp. Method and apparatus for selectively disabling termination circuitry
US9887552B2 (en) * 2013-03-14 2018-02-06 Analog Devices, Inc. Fine timing adjustment method
US10468087B2 (en) * 2016-07-28 2019-11-05 Micron Technology, Inc. Apparatuses and methods for operations in a self-refresh state
US10079594B2 (en) * 2016-10-03 2018-09-18 Infineon Technologies Ag Current reduction for activated load

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07130166A (ja) * 1993-09-13 1995-05-19 Mitsubishi Electric Corp 半導体記憶装置および同期型半導体記憶装置
JP3592386B2 (ja) * 1994-11-22 2004-11-24 株式会社ルネサステクノロジ 同期型半導体記憶装置
JPH09167488A (ja) * 1995-12-18 1997-06-24 Mitsubishi Electric Corp 半導体記憶装置
JP3638167B2 (ja) * 1996-01-08 2005-04-13 川崎マイクロエレクトロニクス株式会社 小振幅信号インタフェイス用双方向バッファ回路
US5627791A (en) * 1996-02-16 1997-05-06 Micron Technology, Inc. Multiple bank memory with auto refresh to specified bank
US5818777A (en) * 1997-03-07 1998-10-06 Micron Technology, Inc. Circuit for implementing and method for initiating a self-refresh mode

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