JPH11186468A - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPH11186468A JPH11186468A JP9352829A JP35282997A JPH11186468A JP H11186468 A JPH11186468 A JP H11186468A JP 9352829 A JP9352829 A JP 9352829A JP 35282997 A JP35282997 A JP 35282997A JP H11186468 A JPH11186468 A JP H11186468A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- base material
- semiconductor element
- resist film
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000007789 sealing Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000004020 conductor Substances 0.000 claims abstract description 27
- 239000000853 adhesive Substances 0.000 claims abstract description 23
- 230000001070 adhesive effect Effects 0.000 claims abstract description 23
- 230000002093 peripheral effect Effects 0.000 claims abstract description 7
- 239000000463 material Substances 0.000 claims description 37
- 239000002245 particle Substances 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims 2
- 239000011347 resin Substances 0.000 abstract description 24
- 229920005989 resin Polymers 0.000 abstract description 24
- 229910000679 solder Inorganic materials 0.000 abstract description 24
- 238000000034 method Methods 0.000 description 8
- 239000000945 filler Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
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- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
するパッケージにおいて、基材と封止樹脂との密着強度
を高め、剥離を生じないパッケージを提供すること。 【構成】 基材1上に導体パターン3を形成し、この基
材1上に、基材1の周辺部を露出させた状態でソルダー
レジスト6を塗布する。このソルダーレジスト6上に接
着剤により半導体素子8を固定する。封止樹脂は、基材
1の周囲のソルダーレジストから露出している部分を含
む基材1上を封止する。
Description
れるパッケージ、特に、基材上に搭載された半導体素子
を樹脂封止する半導体装置に関する。
体回路がその表面に形成された基材上にソルダーレジス
トを導体回路の一部を露出させて形成し、このソルダー
レジスト上に接着剤により半導体素子を固定し、この導
体回路の露出した部分と半導体素子の電極とを接続し、
樹脂にて封止する技術がある。
た従来の半導体装置では、基材上にソルダーレジストを
形成しており、このソルダーレジストは、樹脂との密着
性が悪いため、封止樹脂の剥離という問題があった。
樹脂との間の剥離を抑制することを目的とする。
に、本発明では、半導体装置において、導体回路がその
表面に形成された基材と、基材の周辺部および導体回路
の一部を露出した状態でこの基材を覆うレジスト膜と、
基材上に搭載され、導体回路の露出した部分とその電極
が接続された半導体素子と、半導体素子を基材のレジス
ト膜から露出した部分を含む領域で封止する封止体とを
備えた構成としたものである。
面を参照しながら説明する。図1(a)〜(b)は本発
明の第1実施形態を説明する図であり、図1(a)は平
面図、図1(b)は図1(a)のA−A’線で切断した
断面図である。
シ材からなる基材1を準備する。この基材1は、裏面に
外部と接続する外部端子2と、表面に導体パターン3と
が形成されており、外部端子2と導体パターン3とはバ
イヤホール4により接続されている。この基材1上には
絶縁性樹脂のレジスト層としてソルダーレジスト6が塗
布されている。ここで、ソルダーレジスト6は、導体パ
ターン3の半導体素子と接続される電極5の部分および
基材1の周囲を露出させた状態で半導体素子8を搭載す
る部分に塗布される。塗布する領域としては、半導体素
子8とほぼ同じ面積に塗布する。塗布の方法としては、
例えば基材上に配置されたマスクを介してレジストを塗
布する印刷方式や、基材全面にレジストを塗布した後に
不要部分を露光現像して除去する露光方式等の公知の方
法により行う。
に接着剤7により半導体素子8を固定する。接着剤とし
ては、銀ペーストやエポキシ材等が好ましく、また、接
着テープを用いてもよい。
ーンの電極5とを公知のワイヤボンディング法を用いて
金属細線10により接続する。
を含む基材1を樹脂11にて封止する。封止は、公知の
ポッティングやトランスファーモールドにより行う。
分12で直接基材1に接しているため、ソルダーレジス
ト6が周辺に塗布されている場合に比べて密着強度が高
く、封止樹脂11と基材1との間で樹脂の剥離が起こり
にくくなる。
分に凹凸を設けてもよい。この場合、導体パターン3上
にソルダーレジスト6を形成した後に、基材1の周囲に
ドリル加工することにより0.1mm以上の凹凸を形成す
る。
とにより、基材1と封止樹脂11との接着面積が増え、
強固に基材と封止樹脂とを接着することができ、さらに
剥離がおきにくくなる。
(a)〜(b)を用いて説明する。図3(a)は平面
図、図3(b)は図3(a)のA−A’線で切断した断
面図である。また、同一の構成には同一の符号を付し、
その説明を省略する。
ける接着剤を半導体素子8裏面全面ではなく、部分的に
形成している。ここで、部分的に形成された接着剤13
は、接着剤13間である半導体素子8裏面にも樹脂11
が回り込むように、直径約0.5mmで、互いに1.5〜2mmく
らいの間隔をあけて、所定の高さ約30μmとなるように
形成されている。また、この接着剤13は、所定サイズ
のノズルから吐出することによって、部分的に設けるこ
とができる。
た例を説明したが、接着剤に代えて予めシート状に固め
られたシート状接着剤を用いてもよい。シート状接着剤
を用いた場合は、それぞれのシート状接着剤の厚が一定
となるため、半導体素子8の傾きをなくすことができ、
半導体素子8の厚さ方向のばらつきが低減される。
(a)〜(b)を用いて説明する。図4(a)は平面
図、図4(b)は図4(a)のA−A’線で切断した断
面図である。また、同一の構成には同一の符号を付し、
その説明を省略する。
の基材1を準備し、この基材1上に絶縁性樹脂のレジス
と層としてソルダーレジストを塗布する。ここで、ソル
ダーレジスト15は、導体パターン3の半導体素子と接
続される電極5の部分を露出させた状態で基材1表面に
第1の実施形態と同様の方法で塗布する。
ッチングまたはドリル加工することによりソルダーレジ
スト15表面を凹凸を設ける。この時の凹凸の粗さは、
0.1mm以上が好ましい。
体素子8をソルダーレジスト15上に固定し、半導体素
子8状の電極9と、導体パターンの電極5とを公知のワ
イヤボンディング法を用いて金属細線10により接続
し、この半導体素子8、金属細線10を含む基材1を樹
脂にて封止する。この時、封止する樹脂は、ソルダーレ
ジストの表面に形成された凹凸を含む領域に形成される
ため、封止体11との接着面積が増え、剥離が起こりに
くくなる。また、封止樹脂には、フィラーと呼ばれる粒
子が含まれており、この粒径が一般的には0.5〜0.75mm
である。このため、凹凸の粗さをこの粒径よりも大きな
0.1mm以上とすることにより、フィラーがソルダレジス
トの凹凸に入り込み、より一層接着強度が向上する。
(a)〜(b)を用いて説明する。図5(a)は平面
図、図5(b)は図5(a)のA−A’線で切断した断
面図である。また、同一の構成には同一の符号を付し、
その説明を省略する。
させてソルダーレジスト17を形成する。また、基材1
の端部には、その辺に沿って封止体に含まれるフィラー
の粒径よりも深い、例えば深さ0.1mm以上の複数のザグ
リ部18が設けられている。
けたことにより、封止体11と基材1との接着面積が広
くなり、剥離が起こりにくくなる。このザグリ部は、例
えば図6(a)、(b)に示すように円形でも良く、ま
た、基材1裏面まで貫通させるような形状の貫通穴19
としてもよい。ザグリ部の形状を円形とする場合は、直
径約0.3mm程度が好ましい。
(a)〜(c)を用いて説明する。図7(a)は平面
図、図7(b)は図7(a)のA−A’線で切断した断
面図、図7(c)は個片に分割後の半導体装置を示す図
である。また、同一の構成には同一の符号を付し、その
説明を省略する。
をあけてICチップ8を搭載する。この際、半導体素子
8の下には導電パターン3、ソルダーレジスト6が形成
されている。次に、このような基材1の半導体素子8間
に0.1mm以上の深さのザグリ部20を形成する。ザグリ
部20を形成した後に、半導体素子8を含む基材表面全
面を樹脂からなる封止体11にて封止し、ザグリ部20
を形成した部分を切断し、個片の半導体装置を得る。
を切断することにより、もっとも剥がれやすい半導体装
置周辺部の接着面積を増やすことができ、封止体11と
基材1との剥離がおきにくくなる。
(a)〜(b)を用いて説明する。図8(a)は平面
図、図8(b)は図8(a)のA−A’線で切断した断
面図である。また、同一の構成には同一の符号を付し、
その説明を省略する。
た導体パターン3上のみにソルダーレジスト21を形成
する構成としている。このため、基材1の各導体パター
ン間の部分もソルダーレジストから露出するので、封止
樹脂11と基材1との接着強度はより向上する。また、
導体パターン3は、半導体素子と接続する部分5を除い
てソルダーレジスト21に覆われているので、異物など
によるパターン間のショートなどの不具合もない。
体と基材との間にソルダーレジスト非形成領域、凹凸面
あるいはザグリ部を設けることにより、封止体と基材と
の間が強固に接着され、これらの剥離を抑制できる。
面図である。
る。
面図である。
面図である。
面図である。
および断面図である。
面図である。
面図である。
Claims (17)
- 【請求項1】 導体回路がその表面に形成された基材
と、 前記基材の周辺部および前記導体回路の一部を露出した
状態でこの基材を覆うレジスト膜と、 前記基材上に搭載され、前記導体回路の前記露出した部
分とその電極が接続された半導体素子と、 前記半導体素子を前記基材の前記レジスト膜から露出し
た部分を含む領域で封止する封止体と、 を含むことを特徴とする半導体装置。 - 【請求項2】 請求項1項記載の半導体装置において、
前記基材はさらにこの基材の表裏を貫通する貫通孔と、
裏面に形成された外部電極とを有し、前記導体回路と前
記外部電極とが前記バイヤホールを介して接続されてい
ることを特徴とする。 - 【請求項3】 請求項1項記載の半導体装置において、
前記レジスト膜は前記半導体素子と略同形状であること
を特徴とする。 - 【請求項4】 請求項1項記載の半導体装置において、
前記半導体素子は、前記レジスト膜上に接着剤を介して
固着されていることを特徴とする。 - 【請求項5】 請求項4項記載の半導体装置において、
前記接着剤は、前記半導体素子と前記レジスト膜との間
に部分的に複数箇所設けられ、これら接着剤間に前記封
止体が充填されていることを特徴とする。 - 【請求項6】 請求項4項あるいは5項記載の半導体装
置において、前記接着剤は、シート状接着剤であること
を特徴とする。 - 【請求項7】 請求項1項記載の半導体装置において、
前記レジスト膜から露出している前記基材の周辺部に凹
凸が設けられ、前記封止体はこの凹凸を含む領域で形成
されていることを特徴とする。 - 【請求項8】 請求項1項記載の半導体装置において、
前記レジスト膜から露出している前記基材の周辺部に複
数の凹部が設けられ、前記封止体はこの複数の凹部を含
む領域で形成されていることを特徴とする。 - 【請求項9】 導体回路がその表面に形成された基材
と、 前記導体回路の一部を露出した状態でこの基材を覆うレ
ジスト膜であって、前記基材の周辺部において凹凸部を
備える前記レジスト膜と、 前記基材上に搭載され、前記導体回路の前記露出した部
分とその電極が接続された半導体素子と、 前記半導体素子を前記レジスト膜の前記凹凸部を含む領
域で封止する封止体と、 を含むことを特徴とする半導体装置。 - 【請求項10】 導体回路がその表面に形成され、その
端部に開孔部を有する基材と、 前記導体回路の一部を露出した状態でこの基材を覆うレ
ジスト膜と、 前記基材上に搭載され、前記導体回路の前記露出した部
分とその電極が接続された半導体素子と、 前記半導体素子を前記基材の前記開孔部を含む領域で封
止する封止体と、を含むことを特徴とする半導体装置。 - 【請求項11】 請求項10項記載の半導体装置におい
て、前記基材は略矩形形状をなし、前記開孔部は、前記
基材の辺に沿って複数設けられていることを特徴とす
る。 - 【請求項12】 請求項10項記載の半導体装置におい
て、前記基材は略矩形形状をなし、前記開孔部は、前記
基材の辺に沿って連続的に設けられていることを特徴と
する。 - 【請求項13】 導体回路がその表面に形成された基材
と、 前記導体回路間およびこの導体回路の一部を露出させて
この導体回路を覆うレジスト膜と、 前記基材上に搭載され、前記導体回路の前記露出した部
分とその電極が接続された半導体素子と、 前記半導体素子を前記基材の前記レジスト膜から露出し
た部分を含む領域で封止する封止体と、 を含むことを特徴とする半導体装置。 - 【請求項14】 請求項1項または13項記載の半導体
装置において、前記導体回路は前記基材の表裏面を貫通
する貫通孔を介してこの基材の裏面に形成された外部電
極と接続され、 前記貫通孔上に前記半導体素子が配置されることを特徴
とする半導体装置。 - 【請求項15】 請求項7項または9項に記載の半導体
装置における前記凹凸の凸部間の間隔は前記封止体に含
まれる粒子の粒径よりも大きいことを特徴とする半導体
装置。 - 【請求項16】 請求項8項記載の半導体装置におい
て、前記凹部の大きさは、前記封止体に含まれる粒子の
粒径よりも大きいことを特徴とする半導体装置。 - 【請求項17】 請求項10項記載の半導体装置におい
て、前記開孔部の大きさは、前記封止体に含まれる粒子
の粒径よりも大きいことを特徴とする半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP35282997A JP3638771B2 (ja) | 1997-12-22 | 1997-12-22 | 半導体装置 |
US09/200,964 US6107679A (en) | 1997-12-22 | 1998-11-30 | Semiconductor device |
KR1019980055389A KR100522620B1 (ko) | 1997-12-22 | 1998-12-16 | 반도체장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP35282997A JP3638771B2 (ja) | 1997-12-22 | 1997-12-22 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH11186468A true JPH11186468A (ja) | 1999-07-09 |
JP3638771B2 JP3638771B2 (ja) | 2005-04-13 |
Family
ID=18426729
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Application Number | Title | Priority Date | Filing Date |
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JP35282997A Expired - Lifetime JP3638771B2 (ja) | 1997-12-22 | 1997-12-22 | 半導体装置 |
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---|---|
US (1) | US6107679A (ja) |
JP (1) | JP3638771B2 (ja) |
KR (1) | KR100522620B1 (ja) |
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JP2006313802A (ja) * | 2005-05-09 | 2006-11-16 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP4614818B2 (ja) * | 2005-05-09 | 2011-01-19 | パナソニック株式会社 | 半導体装置およびその製造方法 |
JP2012073233A (ja) * | 2010-08-31 | 2012-04-12 | Mitsumi Electric Co Ltd | センサ装置及び半導体センサ素子の実装方法 |
WO2020100947A1 (ja) * | 2018-11-15 | 2020-05-22 | ローム株式会社 | 半導体装置 |
JPWO2020100947A1 (ja) * | 2018-11-15 | 2021-10-07 | ローム株式会社 | 半導体装置 |
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Also Published As
Publication number | Publication date |
---|---|
KR100522620B1 (ko) | 2006-01-12 |
US6107679A (en) | 2000-08-22 |
JP3638771B2 (ja) | 2005-04-13 |
KR19990063107A (ko) | 1999-07-26 |
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