FR3111471B1 - Substrat de support pour circuit intégré, dispositif électronique, et procédés de production et de conditionnement correspondants. - Google Patents

Substrat de support pour circuit intégré, dispositif électronique, et procédés de production et de conditionnement correspondants. Download PDF

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Publication number
FR3111471B1
FR3111471B1 FR2006208A FR2006208A FR3111471B1 FR 3111471 B1 FR3111471 B1 FR 3111471B1 FR 2006208 A FR2006208 A FR 2006208A FR 2006208 A FR2006208 A FR 2006208A FR 3111471 B1 FR3111471 B1 FR 3111471B1
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Prior art keywords
electronic device
support substrate
packaging
producing
methods
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Expired - Fee Related
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FR2006208A
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English (en)
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FR3111471A1 (fr
Inventor
Richard Rembert
Didier Signoret
Olivier Franiatte
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STMicroelectronics Grenoble 2 SAS
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STMicroelectronics Grenoble 2 SAS
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Priority to FR2006208A priority Critical patent/FR3111471B1/fr
Priority to US17/345,600 priority patent/US20210391227A1/en
Publication of FR3111471A1 publication Critical patent/FR3111471A1/fr
Application granted granted Critical
Publication of FR3111471B1 publication Critical patent/FR3111471B1/fr
Expired - Fee Related legal-status Critical Current
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

Le dispositif électronique comporte un substrat de support ayant une face recouverte d’une couche de vernis épargne (110), au moins une partie (310, 312) de la couche de vernis épargne (110) comportant des rugosités (300, 600) formant une surface d’accroche rugueuse. Le dispositif électronique comporte en outre une puce électronique (400) montée sur le substrat de support (100), et une résine de moulage (500) englobant la puce électronique (400) et recouvrant partiellement ou intégralement la couche de vernis épargne (110). Figure pour l’abrégé : Fig 5
FR2006208A 2020-06-15 2020-06-15 Substrat de support pour circuit intégré, dispositif électronique, et procédés de production et de conditionnement correspondants. Expired - Fee Related FR3111471B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR2006208A FR3111471B1 (fr) 2020-06-15 2020-06-15 Substrat de support pour circuit intégré, dispositif électronique, et procédés de production et de conditionnement correspondants.
US17/345,600 US20210391227A1 (en) 2020-06-15 2021-06-11 Support substrate for integrated circuit, electronic device, and corresponding production and packaging methods

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2006208 2020-06-15
FR2006208A FR3111471B1 (fr) 2020-06-15 2020-06-15 Substrat de support pour circuit intégré, dispositif électronique, et procédés de production et de conditionnement correspondants.

Publications (2)

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FR3111471A1 FR3111471A1 (fr) 2021-12-17
FR3111471B1 true FR3111471B1 (fr) 2022-10-28

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FR2006208A Expired - Fee Related FR3111471B1 (fr) 2020-06-15 2020-06-15 Substrat de support pour circuit intégré, dispositif électronique, et procédés de production et de conditionnement correspondants.

Country Status (2)

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US (1) US20210391227A1 (fr)
FR (1) FR3111471B1 (fr)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03166790A (ja) * 1989-11-27 1991-07-18 Matsushita Electric Works Ltd プリント配線板への印字方法
JP2751501B2 (ja) * 1989-12-25 1998-05-18 富士通株式会社 半導体装置及びその製造方法
JPH08306824A (ja) * 1995-04-28 1996-11-22 Citizen Watch Co Ltd 樹脂封止型半導体装置
JP3638771B2 (ja) * 1997-12-22 2005-04-13 沖電気工業株式会社 半導体装置
JP2019186326A (ja) * 2018-04-05 2019-10-24 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Also Published As

Publication number Publication date
US20210391227A1 (en) 2021-12-16
FR3111471A1 (fr) 2021-12-17

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