JP2017503341A - 電気回路機構を有する構造体内の反りの低減 - Google Patents
電気回路機構を有する構造体内の反りの低減 Download PDFInfo
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Abstract
Description
電気回路機構を含む第1の構造体(例えば、層720、並びに場合によっては1810及び/又は1820)を得る工程であって、第1の構造体は第1の表面(例えば、図7の上部表面)及び第1の表面の反対側にある第2の表面を含み、第1及び第2の表面のうちの少なくとも1つは、反っている第1の領域を含む、工程と、
第1の領域の反りをオーバーバランスさせるために第1の表面上に第1の層(例えば、810)を形成する工程と、
第1の領域の反りを低減するように第1の層を処理する工程と、を含む、製造方法を提供する。
電気回路機構を含む第1の構造体(例えば、層720、並びに場合によっては1810及び/又は1820)を得る工程であって、第1の構造体は第1の表面及び第1の表面の反対側にある第2の表面を含み、第1及び第2の表面のうちの少なくとも1つは、反っている第1の領域を含む、工程と、
タンタルアルミニウム合金の第1の層(例えば、810)を第1の表面上に形成する工程であって、アルミニウムの含有率は重量の10%〜60%であり、反りは第1の層を形成する工程の結果として低減される、工程と、を含む、製造方法を提供する。
電気回路機構を含む第1の部分(例えば、720、並びに場合によっては1810及び/又は1820)であって、第1の部分は第1の表面及び第1の表面の反対側にある第2の表面を含み、第1及び第2の表面のうちの少なくとも1つは第1の領域を含む、第1の部分と、
接着剤を含む、第1の表面上の第1の層(例えば、810)であって、接着剤は、接着剤が第1の領域から剥離される1つ以上の選択された位置を除き、第1の領域全体にわたって第1の層を第1の表面に接合する、第1の層と、を含む、製造物を提供する。
第1の表面、第1の表面の反対側にある第2の表面、及び第1の表面と第2の表面との間にある電気回路機構を含む第1の部分(例えば、720、並びに場合によっては1810及び/又は1820)であって、第1及び第2の表面のうちの1つは第1の領域を含む、第1の部分と、
第1の表面上の第1の層(例えば、810)であって、第1の層は以下の条件(A)及び(B):
(A)第1の層は第1の表面に均一に接合されていない、
(B)第1の層は1つ以上の凹部を含む、
のうちの1つ以上を満たす、第1の層と、を含み、
第1の層が存在しない場合、第1の領域は第1の反りを有し、
第1の層が前記条件(A)及び(B)のうちの1つ以上を満たさない場合、第1の領域は第1の反りと反対の符号の第2の反りを有する、製造物を提供する。
電気回路機構を含む第1の部分(例えば、720、並びに場合によっては1810及び/又は1820)であって、第1の部分は第1の表面及び第1の表面の反対側にある第2の表面を含み、第1及び第2の表面のうちの少なくとも1つは第1の領域を含む、第1の部分と、
第1の表面上の第1の層であって、第1の層はタンタルアルミニウム合金の層であり、アルミニウムの含有率は重量の10%〜60%である、第1の層と、を含む、製造物を提供する。
Claims (31)
- 電気回路機構を含む第1の構造体を得る工程であって、前記第1の構造体は第1の表面及び前記第1の表面の反対側にある第2の表面を含み、前記第1及び第2の表面のうちの少なくとも1つは、反っている第1の領域を含む、工程と、
前記第1の領域の反りをオーバーバランスさせるように前記第1の表面上に第1の層を形成する工程と、
前記第1の領域の反りを低減するように前記第1の層を処理する工程と、
を含む、製造方法。 - 前記第1の層は前記第1の表面に接着接合され、
前記第1の層を処理する工程は、1つ以上の選択された位置で前記第1の層を剥離する工程を含む、請求項1に記載の方法。 - 前記第1の層は、第1のサブ層及び前記第1のサブ層を前記第1の表面に接合する接着剤を含み、前記第1のサブ層は前記接着剤と異なる組成を有する、請求項2に記載の方法。
- 前記剥離する工程は、光及び/又は熱を使用して実行される、請求項2に記載の方法。
- 前記第1の層を処理する工程は、前記第1の層内で相転移を誘起するように前記第1の層の少なくとも一部を加熱する工程を含む、請求項1に記載の方法。
- 前記第1の層を処理する工程は、1つ以上の選択された位置で前記第1の層の1つ以上の部分を除去する工程を含む、請求項1に記載の方法。
- 前記第1の構造体は、前記電気回路機構への接続のための1つ以上のコンタクトパッドを含み、
前記第1の層を処理する工程の後、前記方法は、1つ以上の第2の構造体内の1つ以上の導体線路に前記コンタクトパッドのうちの1つ以上を取り付ける工程を含む、請求項1に記載の方法。 - 前記第1の領域は、前記構造体の第1の側にある前記構造体の領域全体である、請求項1に記載の方法。
- 前記第1の構造体は、1つ以上の半導体集積回路を含み、前記第1の領域は、前記半導体集積回路のうちの1つ以上を含むか又はそれらに直接取り付けられたウェハ若しくはダイの領域である、請求項1に記載の方法。
- 電気回路機構を含む第1の構造体を得る工程であって、前記第1の構造体は第1の表面及び前記第1の表面の反対側にある第2の表面を含み、前記第1及び第2の表面のうちの少なくとも1つは、反っている第1の領域を含む、工程と、
タンタルアルミニウム合金の第1の層を前記第1の表面上に形成する工程であって、前記アルミニウムの含有率は重量の10%〜60%であり、前記反りは前記第1の層を形成する工程の結果として低減される、工程と、
を含む、製造方法。 - 前記第1の層は物理蒸着によって形成される、請求項10に記載の方法。
- 前記第1の層は2μm以下の厚みを有する、請求項10に記載の方法。
- 電気回路機構を含む第1の部分であって、前記第1の部分は第1の表面及び前記第1の表面の反対側にある第2の表面を含み、前記第1及び第2の表面のうちの少なくとも1つは第1の領域を含む、第1の部分と、
接着剤を含む、前記第1の表面上の第1の層であって、前記接着剤は、前記接着剤が前記第1の領域から剥離される1つ以上の選択された位置を除き、前記第1の領域全体にわたって前記第1の層を前記第1の表面に接合する、第1の層と、
を含む、製造物。 - 各前記位置は、前記第1の領域に接合された前記接着剤によって囲まれる、請求項13に記載の製造物。
- 前記第1の層は、第1のサブ層及び前記第1のサブ層を前記第1の表面に接合する接着剤を含み、前記第1のサブ層は前記接着剤と異なる組成を有する、請求項13に記載の製造物。
- 各前記位置での、前記剥離される接着剤の領域の横方向の最大寸法は3μm〜5μmである、請求項13に記載の製造物。
- 前記第1の部分は、1つ以上の第2の構造体内の1つ以上の導体線路に取り付けられた1つ以上のコンタクトパッドを含む、請求項13に記載の製造物。
- 前記第1の領域は、前記第1の部分の第1の側にある前記構造体の領域全体である、請求項13に記載の製造物。
- 前記第1の部分は、1つ以上の半導体集積回路を含み、前記第1の領域は、前記半導体集積回路のうちの1つ以上を含むか又はそれらに直接取り付けられたウェハ若しくはダイの領域である、請求項13に記載の製造物。
- 第1の表面、前記第1の表面の反対側にある第2の表面、及び前記第1の表面と前記第2の表面との間にある電気回路機構を含む第1の部分であって、前記第1及び第2の表面のうちの1つは第1の領域を含む、第1の部分と、
前記第1の表面上の第1の層であって、前記第1の層は以下の条件(A)及び(B):
(A)前記第1の層は前記第1の表面に均一に接合されていない、
(B)前記第1の層は1つ以上の凹部を含む、
のうちの1つ以上を満たす、第1の層と、
を含み、
前記第1の層が存在しない場合、前記第1の領域は第1の反りを有し、
前記第1の層が前記条件(A)及び(B)のうちの前記1つ以上を満たさない場合、前記第1の領域は前記第1の反りと反対の符号の第2の反りを有する、製造物。 - 前記条件(A)及び(B)のうちの前記1つ以上は前記条件(A)からなる、請求項20に記載の製造物。
- 前記条件(A)及び(B)のうちの前記1つ以上は前記条件(B)からなる、請求項20に記載の製造物。
- 前記条件(A)及び(B)のうちの前記1つ以上は前記条件(A)及び(B)からなる、請求項20に記載の製造物。
- 前記第1の部分は、1つ以上の第2の構造体内の1つ以上の導体線路に取り付けられた1つ以上のコンタクトパッドを含む、請求項20に記載の製造物。
- 前記第1の領域は、前記製造物の第1の側の全てである、請求項20に記載の製造物。
- 前記第1の部分は、1つ以上の半導体集積回路を含み、前記第1の領域は、前記半導体集積回路のうちの1つ以上を含むか又はそれらに直接取り付けられたウェハ若しくはダイの領域である、請求項20に記載の製造物。
- 電気回路機構を含む第1の部分であって、前記第1の部分は第1の表面及び前記第1の表面の反対側にある第2の表面を含み、前記第1及び第2の表面のうちの少なくとも1つは第1の領域を含む、第1の部分と、
前記第1の表面上の第1の層であって、前記第1の層はタンタルアルミニウム合金の層であり、前記アルミニウムの含有率は重量の10%〜60%である、第1の層と、
を含む、製造物。 - 前記第1の層は2μm以下の厚みを有する、請求項27に記載の製造物。
- 前記第1の部分は、1つ以上の第2の構造体内の1つ以上の導体線路に取り付けられた1つ以上のコンタクトパッドを含む、請求項27に記載の製造物。
- 前記第1の領域は、前記第1の部分の第1の側にある前記構造体の領域全体である、請求項27に記載の製造物。
- 前記第1の部分は、1つ以上の半導体集積回路を含み、前記第1の領域は、前記半導体集積回路のうちの1つ以上を含むか又はそれらに直接取り付けられたウェハ若しくはダイの領域である、請求項27に記載の製造物。
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PCT/US2014/068162 WO2015084848A2 (en) | 2013-12-03 | 2014-12-02 | Warpage reduction in structures with electrical circuitry |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200078635A (ko) * | 2018-03-14 | 2020-07-01 | 레이던 컴퍼니 | 본딩 웨이퍼의 응력 보상 및 완화 |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9673161B2 (en) * | 2012-08-17 | 2017-06-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonded structures for package and substrate |
US9397051B2 (en) | 2013-12-03 | 2016-07-19 | Invensas Corporation | Warpage reduction in structures with electrical circuitry |
JP7164289B2 (ja) * | 2016-09-05 | 2022-11-01 | 東京エレクトロン株式会社 | 半導体プロセッシング中のオーバレイを制御するための湾曲を制御する応力の位置特定チューニング |
TWI616996B (zh) * | 2016-10-21 | 2018-03-01 | 矽品精密工業股份有限公司 | 半導體組件的回焊方法 |
US10446423B2 (en) | 2016-11-19 | 2019-10-15 | Applied Materials, Inc. | Next generation warpage measurement system |
EP3582295B1 (en) | 2017-10-25 | 2022-11-30 | LG Energy Solution, Ltd. | One-sided electrode with reduced twisting for a secondary battery, and method for producing same |
KR102484394B1 (ko) | 2017-12-06 | 2023-01-03 | 삼성전자주식회사 | 반도체 장치 |
US11081364B2 (en) * | 2019-02-06 | 2021-08-03 | Micron Technology, Inc. | Reduction of crystal growth resulting from annealing a conductive material |
US11031353B2 (en) | 2019-08-23 | 2021-06-08 | Micron Technology, Inc. | Warpage control in microelectronic packages, and related assemblies and methods |
JP2023514497A (ja) * | 2020-01-30 | 2023-04-06 | ラム リサーチ コーポレーション | 局所応力調整のためのuv硬化 |
CN111540750B (zh) * | 2020-04-27 | 2021-07-06 | 长江存储科技有限责任公司 | 3d存储器件的制造方法 |
US12020972B2 (en) * | 2020-04-29 | 2024-06-25 | Semiconductor Components Industries, Llc | Curved semiconductor die systems and related methods |
KR20230137370A (ko) * | 2021-01-26 | 2023-10-04 | 도쿄엘렉트론가부시키가이샤 | 3차원 칩렛 형성을 위한 국부화된 응력 영역 |
US11688642B2 (en) * | 2021-01-26 | 2023-06-27 | Tokyo Electron Limited | Localized stress regions for three-dimension chiplet formation |
US20220336226A1 (en) * | 2021-04-15 | 2022-10-20 | Tokyo Electron Limited | Method of correcting wafer bow using a direct write stress film |
US20230008350A1 (en) * | 2021-07-08 | 2023-01-12 | Tokyo Electron Limited | Method of adjusting wafer shape using multi-directional actuation films |
US20230326767A1 (en) * | 2022-04-08 | 2023-10-12 | Tokyo Electron Limited | Wafer shape control for w2w bonding |
DE102022114911A1 (de) | 2022-06-14 | 2023-12-14 | Delo Industrie Klebstoffe Gmbh & Co. Kgaa | Verfahren zum Herstellen von elektronischen Baugruppen und elektronische Baugruppe auf Wafer-Ebene |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01125917A (ja) * | 1987-11-11 | 1989-05-18 | Sharp Corp | 化合物半導体基板 |
JP2000269337A (ja) * | 1999-03-19 | 2000-09-29 | Toshiba Corp | 半導体装置 |
US20030109082A1 (en) * | 2001-12-06 | 2003-06-12 | Koduri Sreenivasan K. | Back side coating of semiconductor wafers |
US20030162368A1 (en) * | 2002-02-25 | 2003-08-28 | Connell Michael E. | Wafer back side coating to balance stress from passivation layer on front of wafer and be used as a die attach adhesive |
US20070161234A1 (en) * | 2006-01-11 | 2007-07-12 | Rinne Glenn A | Methods of Forming Back Side Layers for Thinned Wafers and Related Structures |
US20070267724A1 (en) * | 2006-05-16 | 2007-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit having stress tuning layer and methods of manufacturing same |
Family Cites Families (52)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4213698A (en) | 1978-12-01 | 1980-07-22 | Bell Telephone Laboratories, Incorporated | Apparatus and method for holding and planarizing thin workpieces |
US4830984A (en) * | 1987-08-19 | 1989-05-16 | Texas Instruments Incorporated | Method for heteroepitaxial growth using tensioning layer on rear substrate surface |
WO1993026041A1 (en) | 1992-06-17 | 1993-12-23 | Harris Corporation | Bonded wafer processing |
US5892281A (en) * | 1996-06-10 | 1999-04-06 | Micron Technology, Inc. | Tantalum-aluminum-nitrogen material for semiconductor devices |
US5885751A (en) | 1996-11-08 | 1999-03-23 | Applied Materials, Inc. | Method and apparatus for depositing deep UV photoresist films |
JP2000164716A (ja) * | 1998-11-26 | 2000-06-16 | Seiko Epson Corp | 半導体装置及びその製造方法 |
US6290274B1 (en) | 1999-04-09 | 2001-09-18 | Tsk America, Inc. | Vacuum system and method for securing a semiconductor wafer in a planar position |
JP3619773B2 (ja) | 2000-12-20 | 2005-02-16 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US7049170B2 (en) | 2003-12-17 | 2006-05-23 | Tru-Si Technologies, Inc. | Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities |
US7202141B2 (en) * | 2004-03-29 | 2007-04-10 | J.P. Sercel Associates, Inc. | Method of separating layers of material |
US7214548B2 (en) | 2004-08-30 | 2007-05-08 | International Business Machines Corporation | Apparatus and method for flattening a warped substrate |
KR100652395B1 (ko) | 2005-01-12 | 2006-12-01 | 삼성전자주식회사 | 다이-휨이 억제된 반도체 소자 및 그 제조방법 |
JP4559866B2 (ja) * | 2005-01-17 | 2010-10-13 | パナソニック株式会社 | 半導体装置の製造方法 |
US7247556B2 (en) * | 2005-02-28 | 2007-07-24 | Agere Systems Inc. | Control of wafer warpage during backend processing |
KR100725364B1 (ko) * | 2005-09-06 | 2007-06-07 | 삼성전자주식회사 | 반도체 칩 패키지 및 그 제조 방법 |
JP4585416B2 (ja) * | 2005-09-22 | 2010-11-24 | 富士通株式会社 | 基板の反り低減構造および基板の反り低減方法 |
EP1914792A2 (en) | 2006-10-17 | 2008-04-23 | Samsung Electronics Co., Ltd. | Method of manufacturing a coil |
US7675182B2 (en) * | 2007-09-27 | 2010-03-09 | Intel Corporation | Die warpage control |
US7618893B2 (en) * | 2008-03-04 | 2009-11-17 | Applied Materials, Inc. | Methods of forming a layer for barrier applications in an interconnect structure |
JP5537802B2 (ja) | 2008-12-26 | 2014-07-02 | ジルトロニック アクチエンゲゼルシャフト | シリコンウエハの製造方法 |
KR20120027237A (ko) * | 2009-04-16 | 2012-03-21 | 수스 마이크로텍 리소그라피 게엠바하 | 웨이퍼 가접합 및 분리를 위한 개선된 장치 |
US8445994B2 (en) | 2009-05-07 | 2013-05-21 | Qualcomm Incorporated | Discontinuous thin semiconductor wafer surface features |
JP2010278040A (ja) | 2009-05-26 | 2010-12-09 | Renesas Electronics Corp | 半導体装置の製造方法および半導体装置 |
US20100314725A1 (en) * | 2009-06-12 | 2010-12-16 | Qualcomm Incorporated | Stress Balance Layer on Semiconductor Wafer Backside |
US8986497B2 (en) * | 2009-12-07 | 2015-03-24 | Ipg Photonics Corporation | Laser lift off systems and methods |
FR2954585B1 (fr) * | 2009-12-23 | 2012-03-02 | Soitec Silicon Insulator Technologies | Procede de realisation d'une heterostructure avec minimisation de contrainte |
US20110221053A1 (en) | 2010-03-11 | 2011-09-15 | Qualcomm Incorporated | Pre-processing to reduce wafer level warpage |
JP5537197B2 (ja) | 2010-03-12 | 2014-07-02 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
DE102010029522B4 (de) | 2010-05-31 | 2022-07-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Verspannungsverringerung beim Einbringen eines Chips in ein Gehäuse mittels eines um den Chip herum ausgebildeten Spannungskompensationsgebiets |
EP2434528A1 (en) * | 2010-09-28 | 2012-03-28 | Nederlandse Organisatie voor toegepast -natuurwetenschappelijk onderzoek TNO | An active carrier for carrying a wafer and method for release |
US9171769B2 (en) * | 2010-12-06 | 2015-10-27 | Stats Chippac, Ltd. | Semiconductor device and method of forming openings through encapsulant to reduce warpage and stress on semiconductor package |
TWI486259B (zh) * | 2010-12-27 | 2015-06-01 | Au Optronics Corp | 可撓式基板結構及其製作方法 |
US8728831B2 (en) | 2010-12-30 | 2014-05-20 | Stmicroelectronics Pte. Ltd. | Reconstituted wafer warpage adjustment |
JP5642628B2 (ja) | 2011-05-27 | 2014-12-17 | 東京エレクトロン株式会社 | 基板反り除去装置、基板反り除去方法及び記憶媒体 |
CN102203927B (zh) | 2011-06-22 | 2013-04-24 | 华为终端有限公司 | 一种器件塑封的方法及其封装结构 |
JP5418564B2 (ja) * | 2011-09-29 | 2014-02-19 | 信越半導体株式会社 | 貼り合わせsoiウェーハの反りを算出する方法、及び貼り合わせsoiウェーハの製造方法 |
US8932901B2 (en) * | 2011-10-31 | 2015-01-13 | Macronix International Co., Ltd. | Stressed phase change materials |
KR20130063564A (ko) | 2011-12-07 | 2013-06-17 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
TWI437672B (zh) | 2011-12-16 | 2014-05-11 | 利用氣體充壓以抑制載板翹曲的載板固定方法 | |
US8757897B2 (en) | 2012-01-10 | 2014-06-24 | Invensas Corporation | Optical interposer |
US8691706B2 (en) | 2012-01-12 | 2014-04-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing substrate warpage in semiconductor processing |
US8900969B2 (en) * | 2012-01-27 | 2014-12-02 | Skyworks Solutions, Inc. | Methods of stress balancing in gallium arsenide wafer processing |
US8642445B2 (en) | 2012-03-29 | 2014-02-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for reducing package warpage |
US8870051B2 (en) | 2012-05-03 | 2014-10-28 | International Business Machines Corporation | Flip chip assembly apparatus employing a warpage-suppressor assembly |
KR101958831B1 (ko) * | 2012-06-08 | 2019-07-02 | 삼성전자주식회사 | 양면 접착성 테이프, 반도체 패키지 및 그 제조 방법 |
TWI520215B (zh) * | 2012-09-19 | 2016-02-01 | 友達光電股份有限公司 | 元件基板及其製造方法 |
US20140124900A1 (en) * | 2012-11-02 | 2014-05-08 | Texas Instruments Incorporated | Through-silicon via (tsv) die and method to control warpage |
US9312193B2 (en) * | 2012-11-09 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress relief structures in package assemblies |
US9586291B2 (en) * | 2012-11-28 | 2017-03-07 | Globalfoundries Inc | Adhesives for bonding handler wafers to device wafers and enabling mid-wavelength infrared laser ablation release |
US9184041B2 (en) * | 2013-06-25 | 2015-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit with backside structures to reduce substrate warp |
US8962449B1 (en) * | 2013-07-30 | 2015-02-24 | Micron Technology, Inc. | Methods for processing semiconductor devices |
US9397051B2 (en) | 2013-12-03 | 2016-07-19 | Invensas Corporation | Warpage reduction in structures with electrical circuitry |
-
2013
- 2013-12-03 US US14/095,704 patent/US9397051B2/en active Active
-
2014
- 2014-12-02 KR KR1020167017662A patent/KR101754347B1/ko active IP Right Grant
- 2014-12-02 JP JP2016536754A patent/JP6058868B1/ja active Active
- 2014-12-02 WO PCT/US2014/068162 patent/WO2015084848A2/en active Application Filing
- 2014-12-02 CN CN201480067772.5A patent/CN105849891B/zh active Active
- 2014-12-02 TW TW103141936A patent/TWI575678B/zh not_active IP Right Cessation
-
2016
- 2016-06-14 US US15/181,861 patent/US9853000B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01125917A (ja) * | 1987-11-11 | 1989-05-18 | Sharp Corp | 化合物半導体基板 |
JP2000269337A (ja) * | 1999-03-19 | 2000-09-29 | Toshiba Corp | 半導体装置 |
US20030109082A1 (en) * | 2001-12-06 | 2003-06-12 | Koduri Sreenivasan K. | Back side coating of semiconductor wafers |
US20030162368A1 (en) * | 2002-02-25 | 2003-08-28 | Connell Michael E. | Wafer back side coating to balance stress from passivation layer on front of wafer and be used as a die attach adhesive |
US20070161234A1 (en) * | 2006-01-11 | 2007-07-12 | Rinne Glenn A | Methods of Forming Back Side Layers for Thinned Wafers and Related Structures |
US20070267724A1 (en) * | 2006-05-16 | 2007-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit having stress tuning layer and methods of manufacturing same |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200078635A (ko) * | 2018-03-14 | 2020-07-01 | 레이던 컴퍼니 | 본딩 웨이퍼의 응력 보상 및 완화 |
KR102515211B1 (ko) | 2018-03-14 | 2023-03-29 | 레이던 컴퍼니 | 본딩 웨이퍼의 응력 보상 및 완화 |
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US20150155241A1 (en) | 2015-06-04 |
US9397051B2 (en) | 2016-07-19 |
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