JPH10313101A5 - - Google Patents
Info
- Publication number
- JPH10313101A5 JPH10313101A5 JP1997119639A JP11963997A JPH10313101A5 JP H10313101 A5 JPH10313101 A5 JP H10313101A5 JP 1997119639 A JP1997119639 A JP 1997119639A JP 11963997 A JP11963997 A JP 11963997A JP H10313101 A5 JPH10313101 A5 JP H10313101A5
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layers
- adjacent
- diffusion
- transistor
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11963997A JP4005663B2 (ja) | 1997-05-09 | 1997-05-09 | 半導体記憶装置 |
| US09/072,724 US6094390A (en) | 1997-05-09 | 1998-05-06 | Semiconductor memory device with column gate and equalizer circuitry |
| US09/587,263 US6288927B1 (en) | 1997-05-09 | 2000-06-05 | Semiconductor memory device with column gate and equalizer circuitry |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11963997A JP4005663B2 (ja) | 1997-05-09 | 1997-05-09 | 半導体記憶装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPH10313101A JPH10313101A (ja) | 1998-11-24 |
| JPH10313101A5 true JPH10313101A5 (enExample) | 2005-03-10 |
| JP4005663B2 JP4005663B2 (ja) | 2007-11-07 |
Family
ID=14766436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11963997A Expired - Fee Related JP4005663B2 (ja) | 1997-05-09 | 1997-05-09 | 半導体記憶装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US6094390A (enExample) |
| JP (1) | JP4005663B2 (enExample) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10108744B8 (de) * | 2001-02-23 | 2008-06-26 | Qimonda Ag | Integrierter DRAM-Speicherbaustein |
| KR100525460B1 (ko) * | 2003-05-23 | 2005-10-31 | (주)실리콘세븐 | 2개의 메모리 블락 사이에 3개의 센스앰프를 가지며,인출과 기입 동작 구간이 분리되는 리프레쉬 동작을수행하는 에스램 호환 메모리 및 그 구동방법 |
| JP4912621B2 (ja) * | 2005-06-07 | 2012-04-11 | 富士通株式会社 | 半導体装置及び半導体装置の配線方法 |
| JP5587141B2 (ja) | 2010-11-05 | 2014-09-10 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
| JP5528987B2 (ja) | 2010-11-11 | 2014-06-25 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
| JP5736224B2 (ja) * | 2011-04-12 | 2015-06-17 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| JP5711033B2 (ja) | 2011-04-12 | 2015-04-30 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
| KR102070623B1 (ko) | 2013-07-09 | 2020-01-29 | 삼성전자 주식회사 | 비트 라인 등화 회로 |
| JP6129004B2 (ja) | 2013-07-18 | 2017-05-17 | ルネサスエレクトロニクス株式会社 | 半導体メモリ |
| KR20150089539A (ko) * | 2014-01-28 | 2015-08-05 | 에스케이하이닉스 주식회사 | 프리차지 회로 및 이를 이용하는 반도체 메모리 장치 |
| JP6373441B2 (ja) * | 2017-04-11 | 2018-08-15 | ルネサスエレクトロニクス株式会社 | 半導体メモリ |
| JP6378391B2 (ja) * | 2017-04-12 | 2018-08-22 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4853897A (en) * | 1986-12-10 | 1989-08-01 | Kabushiki Kaisha Toshiba | Complementary semiconductor memory device |
| US5579256A (en) * | 1988-11-01 | 1996-11-26 | Hitachi, Ltd. | Semiconductor memory device and defect remedying method thereof |
| JPH06268173A (ja) * | 1993-03-15 | 1994-09-22 | Toshiba Corp | 半導体記憶装置 |
| JP3004177B2 (ja) * | 1993-09-16 | 2000-01-31 | 株式会社東芝 | 半導体集積回路装置 |
| US5973369A (en) * | 1997-03-11 | 1999-10-26 | Nec Corporation | SRAM having P-channel TFT as load element with less series-connected high resistance |
-
1997
- 1997-05-09 JP JP11963997A patent/JP4005663B2/ja not_active Expired - Fee Related
-
1998
- 1998-05-06 US US09/072,724 patent/US6094390A/en not_active Expired - Lifetime
-
2000
- 2000-06-05 US US09/587,263 patent/US6288927B1/en not_active Expired - Fee Related
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