JPH10270637A - 複数のｉｃチップを備えた半導体装置の構造 - Google Patents

複数のｉｃチップを備えた半導体装置の構造

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Publication number
JPH10270637A
JPH10270637A JP6854097A JP6854097A JPH10270637A JP H10270637 A JPH10270637 A JP H10270637A JP 6854097 A JP6854097 A JP 6854097A JP 6854097 A JP6854097 A JP 6854097A JP H10270637 A JPH10270637 A JP H10270637A
Authority
JP
Japan
Prior art keywords
chip
chips
bumps
another
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6854097A
Other languages
English (en)
Other versions
JP3349058B2 (ja
Inventor
Tadahiro Morifuji
忠洋 森藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP06854097A priority Critical patent/JP3349058B2/ja
Priority to US09/045,135 priority patent/US6175157B1/en
Publication of JPH10270637A publication Critical patent/JPH10270637A/ja
Application granted granted Critical
Publication of JP3349058B2 publication Critical patent/JP3349058B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

(57)【要約】 【課題】 一つのＩＣチップ２の上面に別のＩＣチップ
４を積み重ねて、この別のＩＣチップを前記一つのＩＣ
チップにその周囲に設けたバンプ４ｂを介して電気的に
接続する場合に、両ＩＣチップ２，４の中心部分の湾曲
変形によって、割れが発生したり、両ＩＣチップ２，４
の回路素子にダメージを及ぼしたりすることを低減す
る。 【手段】 前記両ＩＣチップ２，４の合わせ面のうち前
記各バンプ４ｂより内側の中心部分に捨てバンプ３を設
けて、前記の湾曲変形を小さくする。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、一つのＩＣチップ
の上面に、別のＩＣチップを積み重ねて接続することに
よって、集積度を高めるようにした半導体装置に関する
ものである。
【０００２】
【従来の技術】最近、ＩＣチップを使用した半導体装置
における集積度を高めるために、一つのＩＣチップの上
面に、別のＩＣチップを積み重ね、この別のＩＣチップ
を前記一つのＩＣチップに対して、当該別のＩＣチップ
の周囲に沿って適宜ピッチの間隔で設けた複数個のバン
プにて電気的に接続することが提案されている。
【０００３】
【発明が解決しようとする課題】しかし、一つの上面に
積み重ねた別のＩＣチップを、その周囲に沿って設けた
複数個のバンプにて、前記一つのＩＣチップに対して電
気的に接続するように構成した場合、前記別のＩＣチッ
プのうち前記各バンプより内側の中心部分には、前記一
つのＩＣチップとの間に隙間ができ、換言すると、前記
別のＩＣチップと、その周囲に設けた各バンプにて一つ
のＩＣチップに対して支持されていることにより、この
別のＩＣチップは、当該別のＩＣチップのうち前記各バ
ンプより内側の中心部分に一つのＩＣチップに向かう方
向の外力を受けたときにおいて、前記中心部分が一つの
ＩＣチップに接近するように湾曲変形し易く形態になっ
ており、また、前記一つのＩＣチップも、当該一つのＩ
Ｃチップのうち前記各バンプより内側の中心部分に別の
ＩＣチップに向かう方向の外力を受けたときにおいて、
前記中心部分が別のＩＣチップに接近するように湾曲変
形し易い形態になっているから、前記別のＩＣチップ又
は一つのＩＣチップに割れが発生するばかりか、これら
両ＩＣチップのうち互いに対向する面に形成されている
各種の回路素子にダメージを及ぼすことが多発すると言
う問題があり、特に、これらの問題は、前記一つのＩＣ
チップの上面に積み重ね接続する別のＩＣチップにおけ
る大型化に比例して増大するのであった。
【０００４】本発明は、この問題を解消できるようにし
た半導体装置の構造を提供することを技術的課題とする
ものである。
【０００５】
【課題を解決するための手段】この技術的課題を達成す
るため本発明は、「一つのＩＣチップの上面に別のＩＣ
チップを積み重ね、この別のＩＣチップを前記一つのＩ
Ｃチップに対して、これら両ＩＣチップのうちいずれか
一方又は両方に前記別のＩＣチップの周囲に沿って適宜
間隔で設けたパンプにて電気的に接続して成る半導体装
置において、前記一つのＩＣチップが前記別のＩＣチッ
プに相対する面、及び前記別のＩＣチップが前記一つの
ＩＣチップに相対する面のうちいずれか一方又は両方の
面に、前記各バンプより内側の中心部分に少なくとも一
つ以上の捨てバンプを設ける。」と言う構成にした。
【０００６】
【発明の作用・効果】このように構成することにより、
両ＩＣチップが、当該両ＩＣチップのうち各バンプより
内側の中心部分に外力を受けて、前記中心部分が互いに
接近するように湾曲変形しても、この湾曲変形を、前記
中心部分に少なくとも一つ以上設けた捨てバンプにて小
さい値にとどめることができるか、前記の湾曲変形を皆
無にすることができるのである。
【０００７】従って、本発明によると、一つのＩＣチッ
プの上面に対して別のＩＣチップを積み重ねて、その周
囲に設けた複数個のバンプにて接続する場合において、
両ＩＣチップを大きくしても、これら両ＩＣチップに及
ぶ外力のために、両ＩＣチップが割れること、及び、両
ＩＣチップにおける回路素子にダメージを及ぼすことを
確実に低減できる効果を有する。
【０００８】特に、「請求項２」に記載したように、前
記捨てバンプを、電気接続用バンプに構成することによ
り、両ＩＣチップの相互間を電気的に接続するバンプの
一部を利用して両ＩＣチップの湾曲変形を小さく又は皆
無できるから、バンプの数を多くすることを回避できる
利点がある。
【０００９】
【発明の実施の形態】以下、本発明の実施の形態を、図
１〜図６の図面について説明する。この図において、符
号１は、平面において略矩形に形成したチップマウント
部１ａと、このチップマウント部１ａにおける四つの各
辺から外向きに延びる複数本のリード端子１ｂとを備え
た金属板製のリードフレームを示す。
【００１０】符号２は、前記リードフレーム１における
チップマウント１ａの上面にダイボンディングされる一
つのＩＣチップを示し、この一つのＩＣチップ２は、平
面視において矩形状に形成され、その上面には、中心部
分に図示しない能動素子又は受動素子等のような回路素
子の多数個が形成されていると共に、外側の部分に、外
部への接続用電極パッド１ａの複数個が周囲に沿って適
宜間隔で形成され、この外部への接続用電極パッド１ａ
の内側に、複数個の接続用電極パッド１ｂが周囲に沿っ
て適宜間隔で形成されている。
【００１１】また、符号４は、前記一つのＩＣチップ２
の上面に積み重ねられる別のＩＣチップを示し、この別
のＩＣチップ４は、前記一つのＩＣチップ２よりも小さ
い寸法の矩形状に形成され、その下面には、中心部分に
図示しない能動素子又は受動素子等のような回路素子の
多数個が形成されていると共に、外側の部分に、接続用
電極パッド４ａの複数個が、当該別のＩＣチップ４にお
ける周囲に沿って適宜間隔で形成され、この各接続用電
極パッド４ａの各々には、一つのＩＣチップ２に向かっ
て突出するバンプ４ｂが設けられ、更に、前記別のＩＣ
チップ４の下面のうちその周囲における前記各接続用電
極パッド４ａよりも内側の中心部分には、少なくとも一
つ以上（本実施形態では四個）の捨てバンプ３が、前記
一つのＩＣチップ２に向かって突出するように設けられ
ている。
【００１２】更にまた、符号５は、前記一つのＩＣチッ
プ２における上面と、前記別のＩＣチップ４の下面との
間に介挿した接着フィルムを示し、この両接着フィルム
５には、導電粒子が混入されている。そして、前記一つ
のＩＣチップ２を、前記リードフレーム１におけるチッ
プマウント部１ａの上面に、図３に示すように、一つの
ＩＣチップ２をダイボンディングしたのち、この一つの
ＩＣチップ２の上面に対して、別のＩＣチップ４を、そ
の間に接着フィルム５を挟んで押圧する。
【００１３】この押圧により、前記接着フィルム５は、
両ＩＣチップ２，４に対して接着するから、この接着フ
ィルム５を介して両ＩＣチップ２，４を互いに接着でき
るのであり、これと同時に、この接着フィルム５のうち
別のＩＣチップ４における各接続用電極パッド４ａに設
けたバンプ４ｂに該当する部分が、このバンプ４ｂに
て、図４及び図５に示すように、部分的に強く圧縮変形
されることになり、この強く圧縮変形される部分では、
これに混入した導電粒子が互いに接触することになり、
その結果、前記接着フィルム５のうち前記のように強く
圧縮変形される部分が、厚さ方向についてのみ導電性を
呈することになるから、前記別のＩＣチップ４における
各接続用電極パッド４ａと、前記一つのＩＣチップ２の
上面に設けられている各接続用電極パッド２ｂとの相互
間を、前記接着フィルム５を介して電気的に接続するこ
とができる。
【００１４】この状態で、前記接着フィルム５を乾燥・
硬化することにより、両ＩＣチップ２，４を、その間を
電気的に接続した状態のもとで、一体的に結合できるの
である。この場合において、前記別のＩＣチップ４は、
その周囲に設けた各バンプ４ｂを介して一つのＩＣチッ
プ２に対して支持されると言う形態になっていることに
より、前記別のＩＣチップ４における下面のうちその周
囲の各接続用電極パッド４ａよりも内側の中心部分に捨
てバンプ３が設けられていないときには、前記別のＩＣ
チップ４のうち前記各バンプより内側の中心部分に一つ
のＩＣチップ２に向かう方向の外力を受けたときにおい
て、前記中心部分が一つのＩＣチップ２に接近するよう
に容易に湾曲変形することになるから、当該別のＩＣチ
ップ４又は一つのＩＣチップ２に割れが発生したり、こ
れら両ＩＣチップ２，４のうち互いに対向する面に形成
されている各種の回路素子にダメージを及ぼしたりする
ことが多発するのである。
【００１５】これに対し、前記したように、別のＩＣチ
ップ４における下面のうちその周囲の各接続用電極パッ
ド４ａよりも内側の中心部分に捨てバンプ３を設けると
言う構成にすることにより、両ＩＣチップ２，４が、当
該両ＩＣチップ２，４のうちその周囲における各バンプ
４ｂより内側の中心部分に外力を受けて、前記中心部分
が互いに接近するように湾曲変形しても、この湾曲変形
を、前記中心部分に貼着した軟質フィルム３にて小さい
値にとどめることができるか、或いは、前記の湾曲変形
を皆無にすることができるのである。
【００１６】なお、前記実施の形態は、一つのＩＣチッ
プ２の別のＩＣチップ４との相互間をその周囲において
電気的に接続する各バンプ４ｂを、別のＩＣチップ４に
おける各接続用電極パッド４ａ側に設ける一方、前記両
ＩＣチップ２，４の湾曲変形を小さく規制するか皆無に
するための捨てバンプ３を、別のＩＣチップ４側に設け
た場合を示したが、本発明はこれに限らず、前記バンプ
４ｂを、一つのＩＣチップ２における各接続用電極パッ
ド２ｂ側に設けたり、或いは、一つのＩＣチップ２にお
ける各接続用電極パッド２ｂと別のＩＣチップ４におけ
る各接続用電極パッド４ａとの両方に設けるようにして
も良く、また、前記捨てバンプ３を、一つのＩＣチップ
２側に貼着したり、或いは、両ＩＣチップ２，４の両方
に設けるように構成しても良いことは言うまでもない。
【００１７】更にまた、前記捨てバンプ３を、前記別の
ＩＣチップ４の周囲に設けた各バンプ４ｂと同様に、両
ＩＣチップ２，４の相互間を電気的に接続するものに構
成しても良いのである。このようにして、一つのＩＣチ
ップ２をリードフレーム１にダイボンディングし、この
一つのＩＣチップ２に対して別にＩＣチップ４を固着す
ると、図６に示すように、前記一つのＩＣチップ２にお
ける周囲の各接続用電極パッド１ａと、リードフレーム
１における各リード端子１ｂとの間を細い金属線６にて
ワイヤボンディングしたのち、前記両ＩＣチップ２，４
の全体を、二点鎖線で示すように、熱硬化性合成樹脂の
トランスファ成形によるパッケージ体７にて密封する。
【００１８】次いで、前記各リード端子１ｂを、リード
フレーム１から切り離したのち、図６に二点鎖線で示す
ように、折り曲げることにより、半導体装置の完成品に
するのである。
【図面の簡単な説明】
【図１】本発明の実施の形態を示す分解斜視図である。
【図２】図１の縦断正面図である。
【図３】リードフレームに対して一つのＩＣチップを固
着した状態を示す縦断正面図である。
【図４】前記一つのＩＣチップに対して別のＩＣチップ
を固着した状態を示す縦断正面図である。
【図５】図４の要部拡大図である。
【図６】半導体装置の縦断正面図である。
【符号の説明】
１ リードフレーム １ｂ リード端子 ２ 一つのＩＣチップ ２ａ，２ｂ 接続用電極パッド ３ 捨てバンプ ４ 別のＩＣチップ ４ａ 接続用電極パッド ４ｂ バンプ ５ 接着フィルム ６ 金属線 ７ パッケージ体

Claims (2)

    【特許請求の範囲】
  1. 【請求項１】一つのＩＣチップの上面に別のＩＣチップ
    を積み重ね、この別のＩＣチップを前記一つのＩＣチッ
    プに対して、これら両ＩＣチップのうちいずれか一方又
    は両方に前記別のＩＣチップの周囲に沿って適宜間隔で
    設けたパンプにて電気的に接続して成る半導体装置にお
    いて、 前記一つのＩＣチップが前記別のＩＣチップに相対する
    面、及び前記別のＩＣチップが前記一つのＩＣチップに
    相対する面のうちいずれか一方又は両方の面に、前記各
    バンプより内側の中心部分に少なくとも一つ以上の捨て
    バンプを設けたことを特徴とする複数のＩＣチップを備
    えた半導体装置の構造。
  2. 【請求項２】前記「請求項１」において、捨てバンプの
    一部又は全部を、電気接続用のバンプに構成したことを
    特徴とする複数のＩＣチップを備えた半導体装置の構
    造。
JP06854097A 1997-03-21 1997-03-21 複数のｉｃチップを備えた半導体装置の構造 Expired - Fee Related JP3349058B2 (ja)

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US09/045,135 US6175157B1 (en) 1997-03-21 1998-03-20 Semiconductor device package for suppressing warping in semiconductor chips

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