JPH10112181A5 - - Google Patents
Info
- Publication number
- JPH10112181A5 JPH10112181A5 JP1996267277A JP26727796A JPH10112181A5 JP H10112181 A5 JPH10112181 A5 JP H10112181A5 JP 1996267277 A JP1996267277 A JP 1996267277A JP 26727796 A JP26727796 A JP 26727796A JP H10112181 A5 JPH10112181 A5 JP H10112181A5
- Authority
- JP
- Japan
- Prior art keywords
- selection level
- memory device
- semiconductor memory
- level
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8267277A JPH10112181A (ja) | 1996-10-08 | 1996-10-08 | 半導体記憶装置 |
| US08/822,981 US5982701A (en) | 1996-10-08 | 1997-03-21 | Semiconductor memory device with reduced inter-band tunnel current |
| KR1019970010206A KR100245179B1 (ko) | 1996-10-08 | 1997-03-25 | 반도체 기억 장치 |
| TW086104683A TW325571B (en) | 1996-10-08 | 1997-04-11 | Semiconductor memory device with reduced inter-band tunnel current |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8267277A JPH10112181A (ja) | 1996-10-08 | 1996-10-08 | 半導体記憶装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10112181A JPH10112181A (ja) | 1998-04-28 |
| JPH10112181A5 true JPH10112181A5 (enExample) | 2004-08-26 |
Family
ID=17442609
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8267277A Pending JPH10112181A (ja) | 1996-10-08 | 1996-10-08 | 半導体記憶装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5982701A (enExample) |
| JP (1) | JPH10112181A (enExample) |
| KR (1) | KR100245179B1 (enExample) |
| TW (1) | TW325571B (enExample) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000045361A (ko) * | 1998-12-30 | 2000-07-15 | 김영환 | 워드라인 구동장치 |
| US6198670B1 (en) * | 1999-06-22 | 2001-03-06 | Micron Technology, Inc. | Bias generator for a four transistor load less memory cell |
| JP3948183B2 (ja) * | 2000-02-24 | 2007-07-25 | 富士通株式会社 | 半導体記憶装置 |
| KR100655279B1 (ko) | 2000-12-14 | 2006-12-08 | 삼성전자주식회사 | 불휘발성 반도체 메모리 장치 |
| US6785186B2 (en) * | 2002-08-21 | 2004-08-31 | Micron Technology, Inc. | Design of an high speed xdecoder driving a large wordline load consuming less switching current for use in high speed syncflash memory |
| US7301849B2 (en) * | 2003-07-11 | 2007-11-27 | Texas Instruments Incorporated | System for reducing row periphery power consumption in memory devices |
| JP5151106B2 (ja) * | 2006-09-27 | 2013-02-27 | 富士通セミコンダクター株式会社 | 半導体メモリおよびシステム |
| JP2008135099A (ja) | 2006-11-27 | 2008-06-12 | Elpida Memory Inc | 半導体記憶装置 |
| JP4962206B2 (ja) * | 2007-08-10 | 2012-06-27 | 富士通セミコンダクター株式会社 | 半導体記憶装置及びワードデコーダ制御方法 |
| KR100968155B1 (ko) * | 2008-10-02 | 2010-07-06 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
| FR2959057B1 (fr) * | 2010-04-20 | 2012-07-20 | St Microelectronics Crolles 2 | Dispositif de memoire vive dynamique avec circuiterie amelioree de commande des lignes de mots. |
| KR20160149845A (ko) * | 2015-06-19 | 2016-12-28 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR940008722B1 (ko) * | 1991-12-04 | 1994-09-26 | 삼성전자 주식회사 | 반도체 메모리 장치의 워드라인 드라이버 배열방법 |
| JPH0684354A (ja) * | 1992-05-26 | 1994-03-25 | Nec Corp | 行デコーダ回路 |
| JP2842181B2 (ja) * | 1993-11-04 | 1998-12-24 | 日本電気株式会社 | 半導体メモリ装置 |
| JP3636233B2 (ja) * | 1995-12-27 | 2005-04-06 | 富士通株式会社 | ワードドライバ回路及びそれを利用したメモリ回路 |
-
1996
- 1996-10-08 JP JP8267277A patent/JPH10112181A/ja active Pending
-
1997
- 1997-03-21 US US08/822,981 patent/US5982701A/en not_active Expired - Lifetime
- 1997-03-25 KR KR1019970010206A patent/KR100245179B1/ko not_active Expired - Lifetime
- 1997-04-11 TW TW086104683A patent/TW325571B/zh not_active IP Right Cessation
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6233180B1 (en) | Device for determining the validity of word line conditions and for delaying data sensing operation | |
| KR920013456A (ko) | 반도체 기억장치 | |
| JP2008521157A5 (enExample) | ||
| KR920006982A (ko) | 전력-온 리세트 제어 방식의 래치형 행 라인 리피터를 구비한 반도체 메모리 | |
| US10204660B2 (en) | Memory device with strap cells | |
| JPH10112181A5 (enExample) | ||
| JP6192209B2 (ja) | ワードレベルのパワーゲーティングを有するメモリ | |
| KR960005618A (ko) | 반도체 기억장치 | |
| EP1794756B1 (en) | Memory control with selective retention | |
| KR960030409A (ko) | 반도체 기억장치 | |
| JP4083908B2 (ja) | マルチ−ビットデータを貯蔵するための半導体メモリ装置 | |
| KR100245179B1 (ko) | 반도체 기억 장치 | |
| EP1170749B1 (en) | Semiconductor device | |
| CN103794248A (zh) | 多栅极存储器的控制栅极字线驱动器电路 | |
| JPH02502769A (ja) | トランジスタ・ブレークダウン保護回路 | |
| JP2511910B2 (ja) | 半導体記憶装置 | |
| US6859388B1 (en) | Circuit for write field disturbance cancellation in an MRAM and method of operation | |
| KR100543310B1 (ko) | 플래쉬 메모리 소자 | |
| JPH02168494A (ja) | 半導体記憶回路 | |
| JP4290618B2 (ja) | 不揮発性メモリ及びその動作方法 | |
| US6473347B2 (en) | Semiconductor device having memory with effective precharging scheme | |
| JP2001035167A (ja) | 半導体集積回路 | |
| JPH09161481A5 (enExample) | ||
| KR940008720B1 (ko) | 반도체메모리장치 | |
| US10891992B1 (en) | Bit-line repeater insertion architecture |