TW325571B - Semiconductor memory device with reduced inter-band tunnel current - Google Patents

Semiconductor memory device with reduced inter-band tunnel current

Info

Publication number
TW325571B
TW325571B TW086104683A TW86104683A TW325571B TW 325571 B TW325571 B TW 325571B TW 086104683 A TW086104683 A TW 086104683A TW 86104683 A TW86104683 A TW 86104683A TW 325571 B TW325571 B TW 325571B
Authority
TW
Taiwan
Prior art keywords
memory device
semiconductor memory
tunnel current
band tunnel
reduced inter
Prior art date
Application number
TW086104683A
Other languages
English (en)
Chinese (zh)
Inventor
Satoshi Eto
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of TW325571B publication Critical patent/TW325571B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
TW086104683A 1996-10-08 1997-04-11 Semiconductor memory device with reduced inter-band tunnel current TW325571B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8267277A JPH10112181A (ja) 1996-10-08 1996-10-08 半導体記憶装置

Publications (1)

Publication Number Publication Date
TW325571B true TW325571B (en) 1998-01-21

Family

ID=17442609

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086104683A TW325571B (en) 1996-10-08 1997-04-11 Semiconductor memory device with reduced inter-band tunnel current

Country Status (4)

Country Link
US (1) US5982701A (enExample)
JP (1) JPH10112181A (enExample)
KR (1) KR100245179B1 (enExample)
TW (1) TW325571B (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000045361A (ko) * 1998-12-30 2000-07-15 김영환 워드라인 구동장치
US6198670B1 (en) * 1999-06-22 2001-03-06 Micron Technology, Inc. Bias generator for a four transistor load less memory cell
JP3948183B2 (ja) * 2000-02-24 2007-07-25 富士通株式会社 半導体記憶装置
KR100655279B1 (ko) 2000-12-14 2006-12-08 삼성전자주식회사 불휘발성 반도체 메모리 장치
US6785186B2 (en) * 2002-08-21 2004-08-31 Micron Technology, Inc. Design of an high speed xdecoder driving a large wordline load consuming less switching current for use in high speed syncflash memory
US7301849B2 (en) * 2003-07-11 2007-11-27 Texas Instruments Incorporated System for reducing row periphery power consumption in memory devices
JP5151106B2 (ja) * 2006-09-27 2013-02-27 富士通セミコンダクター株式会社 半導体メモリおよびシステム
JP2008135099A (ja) 2006-11-27 2008-06-12 Elpida Memory Inc 半導体記憶装置
JP4962206B2 (ja) * 2007-08-10 2012-06-27 富士通セミコンダクター株式会社 半導体記憶装置及びワードデコーダ制御方法
KR100968155B1 (ko) * 2008-10-02 2010-07-06 주식회사 하이닉스반도체 반도체 메모리 장치
FR2959057B1 (fr) * 2010-04-20 2012-07-20 St Microelectronics Crolles 2 Dispositif de memoire vive dynamique avec circuiterie amelioree de commande des lignes de mots.
KR20160149845A (ko) * 2015-06-19 2016-12-28 에스케이하이닉스 주식회사 반도체 메모리 장치

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940008722B1 (ko) * 1991-12-04 1994-09-26 삼성전자 주식회사 반도체 메모리 장치의 워드라인 드라이버 배열방법
JPH0684354A (ja) * 1992-05-26 1994-03-25 Nec Corp 行デコーダ回路
JP2842181B2 (ja) * 1993-11-04 1998-12-24 日本電気株式会社 半導体メモリ装置
JP3636233B2 (ja) * 1995-12-27 2005-04-06 富士通株式会社 ワードドライバ回路及びそれを利用したメモリ回路

Also Published As

Publication number Publication date
JPH10112181A (ja) 1998-04-28
KR100245179B1 (ko) 2000-02-15
US5982701A (en) 1999-11-09
KR19980032066A (ko) 1998-07-25

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees