JPH09512386A - 接着用フリップチップ集積回路装置のための柔軟性導電性接続バンプ及びその形成方法 - Google Patents
接着用フリップチップ集積回路装置のための柔軟性導電性接続バンプ及びその形成方法Info
- Publication number
- JPH09512386A JPH09512386A JP7521440A JP52144095A JPH09512386A JP H09512386 A JPH09512386 A JP H09512386A JP 7521440 A JP7521440 A JP 7521440A JP 52144095 A JP52144095 A JP 52144095A JP H09512386 A JPH09512386 A JP H09512386A
- Authority
- JP
- Japan
- Prior art keywords
- polymer
- bump
- bumps
- layer
- flexible
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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Classifications
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.電気的接続端子を電気的接続点に広範囲で柔軟に接続するための前記電気 的接続端子を有するベース上への導電性の柔軟性バンプを形成する方法であって 、 ポリマバンプを前記電気的接続端子の所定の位置上に形成する工程と、 当該ポリマバンプを覆いかつ前記電気的接続端子に対する電気的接続を形成す るための延性を有する金属をその上にプレーティングするためのポリマバンプを 含む所定の領域を規定する工程と、 延性を有する金属層を、ポリマバンプ上及び前記電気的接続端子の一部の上に 、広範囲で柔軟に電気的接続端子と電気的接続点との間を接続可能な電気的接続 を形成するために、プレーティングする工程と からなる方法。 2.請求の範囲第1項記載の方法において、前記規定工程は、触媒作用を及ぼ すようにされたポリマバンプを形成するために前記ポリマバンプを触媒化する工 程からなり、更に、前記プレーティング工程は、前記触媒作用を及ぼすようにさ れたポリマバンプを非電気的にプレーティングする工程からなる方法。 3.請求の範囲第1項記載の方法において、前記ポリマバンプ形成工程は、ウ ェットエッチプロセスを用いて前記ポリマバンプを形成する工程からなる方法。 4.請求の範囲第1項記載の方法において、前記ポリマバンプは予め混合され た触媒を有するポリマ材料からなり、更に、前記プレーティング工程は前記 予め混合された触媒を有する前記ポリマバンプを非電気的にプレーティングする 工程からなる方法。 5.請求の範囲第1項記載の方法において、前記ポリマバンプ形成工程は、フ ォトイメージ可能なポリマからポリマバンプを形成する工程からなる方法。 6.請求の範囲第5項記載の方法において、前記規定工程は、触媒作用を及ぼ すようにされたポリマバンプを形成するために前記ポリマバンプを触媒化する工 程からなり、更に、前記プレーティング工程は、前記触媒作用を及ぼすようにさ れたポリマバンプを非電気的にプレーティングする工程からなる方法。 7.請求の範囲第1項記載の方法において、前記方法は更に、 集積回路ウェハ上に延性を有する金属を堆積する工程と、 集積回路ウェハ上に、前記ポリマバンプを覆う延性を有する金属の層、及び、 延性を有する金属の層の一部である所定の領域を規定するために、フォトレジス ト層を形成する工程と、 延性を有する金属の層の残された部分を除去する工程と からなる方法。 8.請求の範囲第1項記載の方法において、前記ポリマバンプは予め混合され た触媒を有するポリマ材料からなり、更に、前記プレーティング工程は、予め混 合された触媒を有するポリマバンプを非電気的にプレーティングする工程からな る方法。 9.電子装置の組立体であって、 電気的接続点を有する電気的装置と、 当該ベース上の電気的接続端子に電気的に接続された導電性の柔軟性バンプを 有するベースと、 前記ベースを前記電気的装置に接続して、前記導電性の柔軟性バンプを前記電 気的接続点に広範囲で電気的に接続する接着剤と からなり、 広範囲で柔軟性前記導電性の柔軟性バンプは、前記電気的接続端子を電気的接 続点及び前記電気的装置に接続し、 前記導電性の柔軟性バンプは、 電気的接続端子の所定の位置上のポリマバンプと、 ポリマバンプ及び電気的接続端子の一部の上にプレートされた延性を有する金 属の層とからなり、 前記ポリマバンプと電気的接続端子とが、電気的接続端子と電気的接続点との 間を接続可能とする、広範囲で柔軟性電気的接続を形成する組立体。 10.導電性の柔軟性バンプを、少なくとも1個の柔軟性バンプに接続するた めの電気的接続を有するベース上に形成する方法であって、 前記電気的接続上にポリマバンプを形成する工程と、 前記少なくとも1個の電気的接続に電気的に接続する導電性の金属薄膜層を、 前記ベース上及びポリマバンプ上に非電気的にプレーティングする工程と、 前 記導電性の金属薄膜層上に、前記柔軟性バンプの表面領域に対応する所定の大き さの開口を有するフォトレジストマスクの層を形成する工程と、 延性を有する金属の層を、フォトレジストマスクによって規定された表面領域 上に、延性を有する金属の層とポリマバンプ及び電気的接続上の薄い導電性の金 属層の一部とからなる導電性の金属層を形成するために電気プレーティン グする工程と、 フォトレジストマスクを、前記導電性の金属薄膜層の残された部分を露出させ るために除去する工程と、 導電性の金属薄膜層を除去する工程と からなる方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US08/195,434 | 1994-02-14 | ||
US08/195,434 US5508228A (en) | 1994-02-14 | 1994-02-14 | Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same |
PCT/US1995/002109 WO1995022172A1 (en) | 1994-02-14 | 1995-02-13 | Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same |
Publications (1)
Publication Number | Publication Date |
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JPH09512386A true JPH09512386A (ja) | 1997-12-09 |
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ID=22721410
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP7521440A Pending JPH09512386A (ja) | 1994-02-14 | 1995-02-13 | 接着用フリップチップ集積回路装置のための柔軟性導電性接続バンプ及びその形成方法 |
Country Status (6)
Country | Link |
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US (1) | US5508228A (ja) |
EP (1) | EP0745270A4 (ja) |
JP (1) | JPH09512386A (ja) |
KR (1) | KR100323082B1 (ja) |
AU (1) | AU1847295A (ja) |
WO (1) | WO1995022172A1 (ja) |
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JP2007512707A (ja) * | 2003-11-26 | 2007-05-17 | アバゴ・テクノロジーズ・ジェネラル・アイピー(シンガポール)プライベート・リミテッド | 基板間においてプレスされるコンプライアント素子を有するデバイス |
JP2007227828A (ja) * | 2006-02-27 | 2007-09-06 | Epson Imaging Devices Corp | 電気光学装置、実装構造体、電気光学装置の製造方法及び電子機器 |
US7402508B2 (en) | 2003-06-13 | 2008-07-22 | Seiko Epson Corporation | Bump structure and method of manufacturing the same, and mounting structure for IC chip and circuit board |
US8207056B2 (en) | 2005-03-23 | 2012-06-26 | Seiko Epson Corporation | Method for manufacturing semiconductor device, and method and structure for implementing semiconductor device |
JP2013030789A (ja) * | 2012-09-10 | 2013-02-07 | Seiko Epson Corp | 実装構造体及び実装構造体の製造方法 |
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EP0827190A3 (en) * | 1994-06-24 | 1998-09-02 | Industrial Technology Research Institute | Bump structure and methods for forming this structure |
US6870272B2 (en) * | 1994-09-20 | 2005-03-22 | Tessera, Inc. | Methods of making microelectronic assemblies including compliant interfaces |
US6284563B1 (en) * | 1995-10-31 | 2001-09-04 | Tessera, Inc. | Method of making compliant microelectronic assemblies |
US6211572B1 (en) * | 1995-10-31 | 2001-04-03 | Tessera, Inc. | Semiconductor chip package with fan-in leads |
US6008072A (en) * | 1995-12-27 | 1999-12-28 | Industrial Technology Research Institute | Tape automated bonding method |
US5989993A (en) * | 1996-02-09 | 1999-11-23 | Elke Zakel | Method for galvanic forming of bonding pads |
US6558979B2 (en) * | 1996-05-21 | 2003-05-06 | Micron Technology, Inc. | Use of palladium in IC manufacturing with conductive polymer bump |
JP2891184B2 (ja) * | 1996-06-13 | 1999-05-17 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US6881611B1 (en) | 1996-07-12 | 2005-04-19 | Fujitsu Limited | Method and mold for manufacturing semiconductor device, semiconductor device and method for mounting the device |
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- 1995-02-13 EP EP95910308A patent/EP0745270A4/en not_active Withdrawn
- 1995-02-13 KR KR1019960704510A patent/KR100323082B1/ko not_active IP Right Cessation
- 1995-02-13 AU AU18472/95A patent/AU1847295A/en not_active Abandoned
- 1995-02-13 WO PCT/US1995/002109 patent/WO1995022172A1/en not_active Application Discontinuation
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US7402508B2 (en) | 2003-06-13 | 2008-07-22 | Seiko Epson Corporation | Bump structure and method of manufacturing the same, and mounting structure for IC chip and circuit board |
JP2007512707A (ja) * | 2003-11-26 | 2007-05-17 | アバゴ・テクノロジーズ・ジェネラル・アイピー(シンガポール)プライベート・リミテッド | 基板間においてプレスされるコンプライアント素子を有するデバイス |
JP4664307B2 (ja) * | 2003-11-26 | 2011-04-06 | アバゴ・テクノロジーズ・ジェネラル・アイピー(シンガポール)プライベート・リミテッド | 基板間においてプレスされるコンプライアント素子を有するデバイス |
US8207056B2 (en) | 2005-03-23 | 2012-06-26 | Seiko Epson Corporation | Method for manufacturing semiconductor device, and method and structure for implementing semiconductor device |
JP2007227828A (ja) * | 2006-02-27 | 2007-09-06 | Epson Imaging Devices Corp | 電気光学装置、実装構造体、電気光学装置の製造方法及び電子機器 |
JP4631742B2 (ja) * | 2006-02-27 | 2011-02-16 | エプソンイメージングデバイス株式会社 | 電気光学装置、実装構造体、電気光学装置の製造方法及び電子機器 |
JP2013030789A (ja) * | 2012-09-10 | 2013-02-07 | Seiko Epson Corp | 実装構造体及び実装構造体の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP0745270A1 (en) | 1996-12-04 |
AU1847295A (en) | 1995-08-29 |
KR100323082B1 (ko) | 2002-06-24 |
US5508228A (en) | 1996-04-16 |
WO1995022172A1 (en) | 1995-08-17 |
EP0745270A4 (en) | 1999-08-11 |
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