AU1847295A - Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same - Google Patents

Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same

Info

Publication number
AU1847295A
AU1847295A AU18472/95A AU1847295A AU1847295A AU 1847295 A AU1847295 A AU 1847295A AU 18472/95 A AU18472/95 A AU 18472/95A AU 1847295 A AU1847295 A AU 1847295A AU 1847295 A AU1847295 A AU 1847295A
Authority
AU
Australia
Prior art keywords
methods
integrated circuit
circuit device
flip chip
chip integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU18472/95A
Inventor
Thomas A Bishop
Mark R Breen
Diana Carter Duane
Robert W Froehlich
Randy L German
Todd H Herder
Kathryn V Keswick
Chung J Lee
Richard D Nelson
Ernest R Nolan
Kimcuc T Tran
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microelectronics and Computer Technology Corp
Original Assignee
Microelectronics and Computer Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microelectronics and Computer Technology Corp filed Critical Microelectronics and Computer Technology Corp
Publication of AU1847295A publication Critical patent/AU1847295A/en
Abandoned legal-status Critical Current

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    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19042Component type being an inductor
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/903Catalyst aided deposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
AU18472/95A 1994-02-14 1995-02-13 Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same Abandoned AU1847295A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US195434 1994-02-14
US08/195,434 US5508228A (en) 1994-02-14 1994-02-14 Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same
PCT/US1995/002109 WO1995022172A1 (en) 1994-02-14 1995-02-13 Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same

Publications (1)

Publication Number Publication Date
AU1847295A true AU1847295A (en) 1995-08-29

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AU18472/95A Abandoned AU1847295A (en) 1994-02-14 1995-02-13 Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same

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US (1) US5508228A (en)
EP (1) EP0745270A4 (en)
JP (1) JPH09512386A (en)
KR (1) KR100323082B1 (en)
AU (1) AU1847295A (en)
WO (1) WO1995022172A1 (en)

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JPH09512386A (en) 1997-12-09
US5508228A (en) 1996-04-16
EP0745270A1 (en) 1996-12-04
WO1995022172A1 (en) 1995-08-17
KR100323082B1 (en) 2002-06-24
EP0745270A4 (en) 1999-08-11

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