CN100356559C - Crystal coated packing structure and its mfg method - Google Patents
Crystal coated packing structure and its mfg method Download PDFInfo
- Publication number
- CN100356559C CN100356559C CNB031575595A CN03157559A CN100356559C CN 100356559 C CN100356559 C CN 100356559C CN B031575595 A CNB031575595 A CN B031575595A CN 03157559 A CN03157559 A CN 03157559A CN 100356559 C CN100356559 C CN 100356559C
- Authority
- CN
- China
- Prior art keywords
- substrate
- flip chip
- packaging structure
- chip packaging
- metal level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
The present invention relates to a crystal coated encapsulation structure and a manufacture method. The crystal coated encapsulation structure comprises a structure of an elastic convex block combined with a substrate to form the crystal coated encapsulation structure, wherein the structure of an elastic convex block is composed of a macromolecule convex block and a metal layer and is formed on conductive contacts on the surface of an electronic assembly; the macromolecule convex block has an upper surface, a lower surface and one or more than one side surfaces; the side surface of the macromolecule convex block is connected with the upper surface and the lower surface; the lower surface is attached to the conductive contacts; the metal layer is covered on the upper surface and extends to conduct the conductive contacts through the side surface in order to form vertical electrical connection; the side surface does not complete cover the metal layer in order to isolate the lateral electric conduction of the metal layer. In such a way, a short-circuit phenomenon among the contacts generated by the collection of conductive particles of anisotropy conductive adhesion agent and wide and fine spacing of fine wires is stopped.
Description
Technical field
The present invention relates to a kind of flip chip packaging structure and manufacture method thereof, relate in particular to a kind of formed flip chip packaging structure of application elastic projection structure and manufacture method thereof.
Background technology
Along with electronic product synchronously towards the development trend of light, thin, short, little, high speed and high mechanization, and make the semiconductor subassembly encapsulation technology improve constantly for the requirement that increases assembly reliability, density and minimizing size of components aspect, so conventional wire bonding method (wire bonding) is replaced by Flip-Chip Using technology (flip-chip) gradually.
The Flip-Chip Using technology is with the composition surface formation joint sheet (pad) of chip and substrate or projection (bump) is to replace the existing employed lead frame of encapsulation technology (lead frame).Realize circuit turn-on through projection and joint sheet between the composition surface of direct pressing chip and substrate, can reduce the electric signal transmission range between chip and substrate, be applicable to the encapsulation of high-velocity electrons assembly.Existing flip chip mounting method is to form projection connected structures such as (bump) on the surface of chip and substrate, then at substrate surface coating solid; Projection with chip and substrate surface passes through the contraposition pressing to finish flip chip packaging structure again.When using solid to be engaged between chip and substrate, because both have serious thermal expansion coefficient difference, when temperature changed, the influence of thermal stress made the bump bond of chip and substrate produce distortion easily.Therefore develop and the elastic conductive projection structure, as No. 5508228 disclosed content of patent of the U.S., be to form projection at the contact place of electronic building brick with macromolecular material, again coated with metal carbonyl coat to form elastic conductive projection, reduce the thermal expansion coefficient difference of contact whereby, reduce the influence of thermal stress.
In addition, for thermal expansion coefficient difference that reduces solid, substrate and chip chamber and the intensity that increases contact, can in the glue material, sneak into suitable non-conductive particle filled composite, particle filled composite can compensate the glue material when variations in temperature, because of the volume change that thermal expansion coefficient difference produced, and the joint strength of increase flip chip packaging structure.And under the situation that thin space engages, can in the glue material, add trickle conducting particles, and reach the conduction of anisotropy (vertical direction); But under the situation of very fine pitch, conducting particles is gathered in the side of contact easily and produces situation of short circuit, makes its applicable live width of institute and pitch-limited.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of flip chip packaging structure and manufacture method thereof, be that elastic projection structure by the electronic building brick surface provides vertical electric connection, the elastic projection structure is made up of macromolecular convex and metal level, the short circuit phenomenon that the design by metal level completely cuts off that the conducting particles because of the anisotropic conductive solid is assembled between the contact, fine rule is wide and produces with thin space.
For achieving the above object, the invention provides a kind of flip chip packaging structure, its characteristics are, include:
One substrate, its surface forms a plurality of joint sheets with the conducting wire as this substrate;
One electronic building brick, its surface has a plurality of conductive junction points;
A plurality of elastic projections, be formed at the conductive junction point on this electronic building brick surface, so that the electric connection of electronic building brick and substrate or other external electronic components to be provided, this elastic projection is formed by a macromolecular convex and a metal level, this macromolecular convex has a upper surface, a lower surface and one or more side, this side connects upper surface and lower surface, this upper surface is engaged in the joint sheet of this substrate surface, this lower surface fits in this conductive junction point, this metal level is covered in this upper surface and extends to this conductive junction point formation vertical electrical connection of conducting by this side again, so that the electric connection of this electronic building brick and this substrate to be provided, at least one side of this macromolecular convex does not cover this metal level, any two elastic projections for adjacency, this elastic projection of one of them is to be adjacent to another elastic projection with the side that does not cover this metal level, with isolated electrically conducting, directly intercept the conducting particles of anisotropic conductive solid, prevent to assemble the short circuit phenomenon that produces because of conducting particles between contact; And
One opposite sex conduction solid, this opposite sex conduction solid is coated the engaging zones of this substrate and this electronic building brick to follow this substrate and this electronic building brick.
Above-mentioned flip chip packaging structure, its characteristics be, this macromolecular convex be shaped as cylinder, hexahedron and polygonal column one of them.
Above-mentioned flip chip packaging structure, its characteristics are, contract 1 micron to 5 microns in the edge of the zone that this metal level covered than this macromolecular convex.
Above-mentioned flip chip packaging structure, its characteristics are that these a plurality of elastic projections become the double arrangement of alternating expression.
Above-mentioned flip chip packaging structure, its characteristics are that this metal level is made up of the outside metal level that coats of a bonding metal layer.
Above-mentioned flip chip packaging structure, its characteristics are that the lower surface of this macromolecular convex has the conductive junction point of a lower metal layer with this electronic building brick of fitting.
Above-mentioned flip chip packaging structure, its characteristics are that this electronic building brick also comprises a polymer protection layer, and described polymer protection layer is arranged at around the described conductive junction point.
Above-mentioned flip chip packaging structure; its characteristics are; this electronic building brick also comprises a polymer protection layer and a grounded metal shielding layer; this grounded metal shielding layer is covered in a diaphragm on electronic building brick surface; this polymer protection layer covers this metal shielding layer, and described diaphragm is covered in around the described conductive junction point.
Above-mentioned flip chip packaging structure, its characteristics are that this metal level extends to this electronic building brick surface periphery to form the contact test structure.
Above-mentioned flip chip packaging structure, its characteristics are that this electronic building brick is a LCD device drive chip.
Above-mentioned flip chip packaging structure, its characteristics be, this substrate be selected from the group that forms by the metal substrate of oxide layer in organic substrate, ceramic substrate, glass substrate, silicon substrate, GaAs substrate and surface one of them.
The present invention also provides a kind of manufacture method of flip chip packaging structure, and its characteristics are that its step includes:
One substrate is provided, and its surface forms a plurality of joint sheets with the conducting wire as this substrate;
One electronic building brick is provided, its surface forms a plurality of conductive junction points, and at a plurality of elastic projections of this conductive junction point surface formation, this elastic projection is formed by a macromolecular convex and a metal level, this macromolecular convex has a upper surface, a lower surface and one or more side, this side connects this upper surface and this lower surface, this metal level is covered in this upper surface and extends to this conductive junction point formation vertical electrical connection of conducting by this side again, and this side of at least one of this macromolecular convex does not cover metal level fully, any two elastic projections for adjacency, this elastic projection of one of them is to be adjacent to another elastic projection with the side that does not cover this metal level, with isolated electrically conducting;
At this substrate surface coating one opposite sex conduction solid;
Make this conductive projection aim at the joint sheet that is pressed on this substrate surface, make this metal level that upper surface covered of this elastic projection be engaged in this joint sheet of this substrate surface, this lower surface fits in this conductive junction point, so that the electric connection of this electronic building brick and this substrate to be provided; And
Solidify this opposite sex conduction solid to engage this assembly and this substrate.
The manufacture method of above-mentioned flip chip packaging structure, its characteristics be, this macromolecular convex be shaped as cylinder, hexahedron and polygonal column one of them.
The manufacture method of above-mentioned flip chip packaging structure, its characteristics are, contract 1 micron to 5 microns in the edge of the zone that this metal level covered than this macromolecular convex.
The manufacture method of above-mentioned flip chip packaging structure, its characteristics are that this metal level is made up of the outside metal level that coats of a bonding metal layer.
The manufacture method of above-mentioned flip chip packaging structure; its characteristics are; this macromolecular convex is the conductive junction point surface that is formed at this electronic building brick with photoetching technique; and forming a polymer protection layer on this electronic building brick surface simultaneously, described polymer protection layer is formed at around the described conductive junction point.
The manufacture method of above-mentioned flip chip packaging structure, its characteristics are, the difference in height of this macromolecular convex and this polymer protection layer is mask (mask) exposure one macromolecule layer by having different penetrances zone, once develops and finishes.
The manufacture method of above-mentioned flip chip packaging structure, its characteristics are that the lower surface of this macromolecular convex has the conductive junction point of a lower metal layer with this electronic building brick of fitting.
The manufacture method of above-mentioned flip chip packaging structure; its characteristics are; this electronic building brick also comprises a polymer protection layer and a grounded metal shielding layer; this grounded metal shielding layer is covered in a diaphragm on this electronic building brick surface; this polymer protection layer covers this metal shielding layer, and described diaphragm is covered in around the described conductive junction point.
The manufacture method of above-mentioned flip chip packaging structure, its characteristics be, the method for this curing glue material is one of them or its combination of hot curing, photocuring and microwave curing.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Figure 1A is the cross-sectional view of first embodiment of the invention;
Figure 1B is the structural representation of the elastic projection of first embodiment of the invention;
Fig. 1 C is the structural representation of the elastic projection of second embodiment of the invention;
Fig. 2 A is the cross-sectional view of third embodiment of the invention;
Fig. 2 B is the cross-sectional view of fourth embodiment of the invention;
Fig. 3 is the connected structure schematic diagram of the present invention's first application examples; And
Fig. 4 is the making flow chart of the present invention's first application examples.
Embodiment
Flip chip packaging structure disclosed in this invention and manufacture method thereof, it is the metal level design that covers by elastic projection and its, the side direction that completely cuts off between the contact electrically connects, to solve the wide short circuit problem that flip chip packaging structure was easy to generate with thin space of fine rule.The elastic projection structure is made up of macromolecular convex and metal level, cooperate different technology and design, the shape of macromolecular convex can be circle, hexahedron or other three-dimensional shape, and the side of its macromolecular convex does not cover metal level fully, with the electrically conducting of isolated its side direction.
The preferred embodiment of the elastic projection structure that the present invention comprised is that a plurality of conductive junction points on the electronic building brick surface form a plurality of elastic projection structures.And be example with the macromolecular convex of hexahedral shape, illustrate that the metal level of macromolecular convex covers situation.
Please refer to Figure 1A, it is the cross-sectional view of first embodiment of the invention, and it comprises: a chip 100, its surface have a plurality of conductive junction points 111, and conductive junction point 111 around covered with protective film 120; 111 applying elastic projections of conductive junction point structure, and by the vertical electric connection of elastic projection structure generation.The elastic projection structure comprises lower metal layer 112, macromolecular convex 110, metal level, and for preventing contact oxidation and the adhesive force that increases metal level and macromolecule collets 110, its metal level is made up of bonding metal layer 113 and metal level 114.Conductive junction point 111 surfaces attach lower metal layer 112, macromolecular convex 110, bonding metal layer 113 and metal level 114 in regular turn, 110 one-tenth hexahedral shape of macromolecular convex, and it has a upper surface, a lower surface and four sides.The lower surface of macromolecular convex fits in lower metal layer 112, metal level is covered in upper surface and extends to conducting conductive junction point 111 to form the vertical electrical connection by two relative sides again, two relative in addition sides do not cover metal level, with the electrically conducting of isolated its side direction.Wherein, when a plurality of elastic projections were arranged, the metal level of its covering was non-conterminous in the elastic projection of its adjacency.
Please refer to Figure 1B, it is the structural representation of the elastic projection of first embodiment of the invention.Characteristic point of the present invention is the design of metal level, its elastic projection structure comprises lower metal layer 112, macromolecular convex 110, bonding metal layer 113 and metal level 114, shown in Figure 1B, the metal level that bonding metal layer 113 and metal level 114 are formed is covered in two sides of macromolecular convex 110 in the cross-over connection mode, two other opposite flank does not then cover metal level, with the electrically conducting of isolated its side direction.
Please refer to Fig. 1 C, it is the structural representation of the elastic projection of second embodiment of the invention.The short circuit that the conducting particles that employed anisotropic conductive solid contains in order effectively to prevent to encapsulate causes, the metal level of being formed except bonding metal layer 113 and metal level 114 is covered in two sides of macromolecular convex 110 in the cross-over connection mode, but the zone that metal level covered is also contracted 1 micron to 5 microns in the edge of higher molecular projection, and reduced scale cun can cooperate the diameter of conducting particles to decide in it.
In addition, different designs can be done in the side that cooperates different projections to arrange the metal level covering, two sides that cover as the metal level of first embodiment also can be adjacent two sides, or metal level covers any three sides to the macromolecule projection by the upper surface of macromolecular convex, and extends to the conducting conductive junction point.The bonding metal layer extends to conducting conductive junction point formation vertical electrical by the side again with the metal level covering upper surface that metal level is formed and is connected, according to different designs, one to three side of macromolecular convex covers metal level, all the other sides then do not cover metal level, with the electrically conducting of isolated its side direction.
In addition, cooperate manufacture method of the present invention, can make the mechanism for testing of polymer protection layer, grounded metal shielding layer and contact qualification rate on the electronic building brick surface simultaneously.
Please refer to Fig. 2 A, it is the generalized section of third embodiment of the invention, chip 100, its surface has a plurality of conductive junction points 111, and conductive junction point 111 around covered with protective film 120.The conductive junction point surface has the elastic projection structure; comprise lower metal layer 112, macromolecular convex 110, bonding metal layer 113 and metal level 114; wherein bonding metal layer 113 extends to diaphragm 120 with metal level 114; can be directly as the mechanism for testing of contact qualification rate; when avoiding carrying out the test of contact qualification rate; the contraposition of test probe and projection and slippage problem also can reduce the influence of probe for projection.Bonding metal layer 113 can be finished in elastic projection structure manufacture process in the lump with the mechanism for testing of the contact qualification rate that forms that metal level 114 extends; and when making the step of macromolecular convex 110; make polymer protection layer 140 on chip 100 surfaces simultaneously, to protect other circuit and surface electronic assembly.
Please refer to Fig. 2 B, it is the generalized section of fourth embodiment of the invention, also can add the grounded metal shielding layer on the electronic building brick surface, to prevent effects such as electromagnetic interference.Shown in Fig. 2 B; polymer protection layer 140 covers metal shielding layer 130; when making metal level 112 on conductive junction point 111 surfaces earlier; make metal shielding layer 130 simultaneously; and be connected with the conductive pad of ground connection on the substrate; when making the step of macromolecular convex 110, make polymer protection layer 140 again on chip 100 surfaces.Wherein while and utilization are with the macromolecular convex with difference in height 110 and polymer protection layer 140 of mask (mask) made; can the eurymeric photosensitive polymer layer be exposed by mask (mask), once develop again and finish with different penetrances zone.
The present invention uses the formed flip chip packaging structure of elastic projection structure, can reach the wide purpose with thin space of fine rule.
Please refer to Fig. 3, it is for the structural representation of the present invention's first application examples.Its flip chip packaging structure is formed by substrate 200, the chip 100 that comprises the elastic projection structure and anisotropic conductive solid 220, anisotropic conductive solid 220 contains conducting particles 221, and the surface of substrate 200 has a plurality of joint sheets 210 with the conducting wire as substrate 200; Chip 100 surfaces have a plurality of conductive junction points 111.Aforesaid a plurality of elastic projection structure is formed at the conductive junction point 111 on chip 100 surfaces and is pressed on a plurality of joint sheets 210 formation and electrically conducts.The upper surface of macromolecular convex 110 is engaged in the joint sheet 210 on substrate 200 surfaces, lower surface fits in conductive junction point 111, bonding metal layer 113 and the metal level that metal level 114 is formed are covered in upper surface and extend to the conducting conductive junction point by one or more side again and form vertical electrical and is connected, so that the electric connection of chip 100 and substrate 200 to be provided.220 of anisotropic conductive solids are coated the engaging zones of substrate 200 and chip 100 to engage, the side of macromolecular convex 110 does not cover metal level fully, the elastic projection structure is adjacent to another projection with the side that does not cover metal level, with the electric connection of isolated side direction.
The manufacture method of flip chip packaging structure please refer to Fig. 4, and it is the making flow chart of the present invention's first application examples, and at first, step 410 provides a substrate, and its surface forms a plurality of joint sheets with the conducting wire as substrate; Secondly, step 420, one chip is provided, a plurality of conductive junction points on its surface form a plurality of elastic projections, elastic projection is formed by macromolecular convex and metal level, the side that it has a upper surface, a lower surface and connects both, and metal level is covered in upper surface and extends to the connection of conducting conductive junction point formation vertical electrical by the side again, the side of this macromolecular convex does not cover metal level fully, with the electrically conducting of isolated its side direction.Then, step 430 is at substrate surface coating anisotropic conductive solid; Step 440 makes conductive projection aim to be pressed on the joint sheet of substrate surface again, makes the upper surface of elastic projection be engaged in the joint sheet of substrate surface, and lower surface fits in conductive junction point, so that the electric connection of electronic building brick and substrate to be provided.At last, step 450 is solidified the anisotropic conductive solid with conjugative component and substrate, promptly forms flip chip packaging structure.
Solid used in the present invention can be selected anisotropic conductive solid or non-conductive solid, electronic building brick can be LCD device drive chip, the optional metal substrate that oxide layer is arranged from organic substrate, ceramic substrate, glass substrate, silicon substrate, GaAs substrate or surface of substrate.
Though preferred embodiment of the present invention openly as mentioned above; yet it is not in order to limit the present invention; any personnel that are familiar with correlation technique; without departing from the spirit and scope of the present invention; the structure of device and manufacture method can be improved through further, but these corresponding changes all should belong to the protection range of the appended claim of invention.
Claims (20)
1, a kind of flip chip packaging structure is characterized in that, includes:
One substrate, its surface forms a plurality of joint sheets with the conducting wire as this substrate;
One electronic building brick, its surface has a plurality of conductive junction points;
A plurality of elastic projections, be formed at the conductive junction point on this electronic building brick surface, this elastic projection is formed by a macromolecular convex and a metal level, this macromolecular convex has a upper surface, a lower surface and two or more side, this side connects upper surface and lower surface, this upper surface is engaged in the joint sheet of this substrate surface, this lower surface fits in this conductive junction point, this metal level is covered in this upper surface and extends to this conductive junction point formation vertical electrical connection of conducting by this side again, so that the electric connection of this electronic building brick and this substrate to be provided, at least one side of this macromolecular convex does not cover this metal level, any two elastic projections for adjacency, this elastic projection of one of them is to be adjacent to another elastic projection with the side that does not cover this metal level, with isolated electrically conducting; And
One anisotropic conductive solid, this anisotropic conductive solid are coated the engaging zones of this substrate and this electronic building brick to follow this substrate and this electronic building brick.
2, flip chip packaging structure according to claim 1 is characterized in that, this macromolecular convex be shaped as hexahedron and polygonal column one of them.
3, flip chip packaging structure according to claim 1 is characterized in that, contracts 1 micron to 5 microns in the edge of the zone that this metal level covered than this macromolecular convex.
4, flip chip packaging structure according to claim 1 is characterized in that, these a plurality of elastic projections become the double arrangement of alternating expression.
5, flip chip packaging structure according to claim 1 is characterized in that, this metal level is made up of the outside metal level that coats of a bonding metal layer.
6, flip chip packaging structure according to claim 1 is characterized in that, the lower surface of this macromolecular convex has the conductive junction point of a lower metal layer with this electronic building brick of fitting.
7, flip chip packaging structure according to claim 1 is characterized in that, this electronic building brick also comprises a polymer protection layer, and described polymer protection layer is arranged at around the described conductive junction point.
8, flip chip packaging structure according to claim 1; it is characterized in that; this electronic building brick also comprises a polymer protection layer and a grounded metal shielding layer; this grounded metal shielding layer is covered on the diaphragm on electronic building brick surface; this polymer protection layer covers this metal shielding layer, and described diaphragm is covered in around the described conductive junction point.
9, flip chip packaging structure according to claim 1 is characterized in that, this metal level extends to this electronic building brick surface periphery to form the contact test structure.
10, flip chip packaging structure according to claim 1 is characterized in that, this electronic building brick is a LCD device drive chip.
11, flip chip packaging structure according to claim 1 is characterized in that, this substrate be selected from the group that organic substrate, ceramic substrate, glass substrate, silicon substrate, GaAs substrate and surface forms by the metal substrate of oxide layer one of them.
12, a kind of manufacture method of flip chip packaging structure is characterized in that, its step includes:
One substrate is provided, and its surface forms a plurality of joint sheets with the conducting wire as this substrate;
One electronic building brick is provided, its surface forms a plurality of conductive junction points, and at a plurality of elastic projections of this conductive junction point surface formation, this elastic projection is formed by a macromolecular convex and a metal level, this macromolecular convex has a upper surface, a lower surface and two or more side, this side connects this upper surface and this lower surface, this metal level is covered in this upper surface and extends to this conductive junction point formation vertical electrical connection of conducting by this side again, and at least one side of this macromolecular convex does not cover metal level, any two elastic projections for adjacency, this elastic projection of one of them is to be adjacent to another elastic projection with the side that does not cover this metal level, with isolated electrically conducting;
Be coated with an anisotropic conductive solid at this substrate surface;
Make this elastic projection aim at the joint sheet that is pressed on this substrate surface, make this metal level that upper surface covered of this elastic projection be engaged in this joint sheet of this substrate surface, this lower surface fits in this conductive junction point, so that the electric connection of this electronic building brick and this substrate to be provided; And
Solidify this anisotropic conductive solid to engage this assembly and this substrate.
13, the manufacture method of flip chip packaging structure according to claim 12 is characterized in that, this macromolecular convex be shaped as hexahedron and polygonal column one of them.
14, the manufacture method of flip chip packaging structure according to claim 12 is characterized in that, contracts 1 micron to 5 microns in the edge of the zone that this metal level covered than this macromolecular convex.
15, the manufacture method of flip chip packaging structure according to claim 12 is characterized in that, this metal level is made up of the outside metal level that coats of a bonding metal layer.
16, the manufacture method of flip chip packaging structure according to claim 12; it is characterized in that; this macromolecular convex is the conductive junction point surface that is formed at this electronic building brick with photoetching technique; and forming a polymer protection layer on this electronic building brick surface simultaneously, described polymer protection layer is formed at around the described conductive junction point.
17, the manufacture method of flip chip packaging structure according to claim 16; it is characterized in that; the difference in height of this macromolecular convex and this polymer protection layer is by having mask exposure one macromolecule layer in different penetrances zone, once developing and finish.
18, the manufacture method of flip chip packaging structure according to claim 12 is characterized in that, the lower surface of this macromolecular convex has the conductive junction point of a lower metal layer with this electronic building brick of fitting.
19, the manufacture method of flip chip packaging structure according to claim 12; it is characterized in that; this electronic building brick also comprises a polymer protection layer and a grounded metal shielding layer; this grounded metal shielding layer is covered on the diaphragm on this electronic building brick surface; this polymer protection layer covers this metal shielding layer, and described diaphragm is covered in around the described conductive junction point.
20, the manufacture method of flip chip packaging structure according to claim 12 is characterized in that, the method for this curing glue material is one of them or its combination of hot curing, photocuring and microwave curing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031575595A CN100356559C (en) | 2003-09-24 | 2003-09-24 | Crystal coated packing structure and its mfg method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031575595A CN100356559C (en) | 2003-09-24 | 2003-09-24 | Crystal coated packing structure and its mfg method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1601737A CN1601737A (en) | 2005-03-30 |
| CN100356559C true CN100356559C (en) | 2007-12-19 |
Family
ID=34660358
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031575595A Expired - Lifetime CN100356559C (en) | 2003-09-24 | 2003-09-24 | Crystal coated packing structure and its mfg method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100356559C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100632472B1 (en) | 2004-04-14 | 2006-10-09 | 삼성전자주식회사 | Microelectronic device chip having a fine pitch bump structure having non-conductive sidewalls, a package thereof, a liquid crystal display device comprising the same, and a manufacturing method thereof |
| CN100580915C (en) * | 2007-02-16 | 2010-01-13 | 南茂科技股份有限公司 | Packaging conductive structure and its manufacturing method |
| CN103096646B (en) * | 2011-10-31 | 2016-01-20 | 健鼎（无锡）电子有限公司 | The manufacture method of the multilager base plate of embedded element |
| WO2020003869A1 (en) * | 2018-06-25 | 2020-01-02 | 株式会社ブイ・テクノロジー | Board mounting method and electronic component mounting board |
| JP2020004939A (en) * | 2018-06-25 | 2020-01-09 | 株式会社ブイ・テクノロジー | Board mounting method and electronic component mounting board |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5508228A (en) * | 1994-02-14 | 1996-04-16 | Microelectronics And Computer Technology Corporation | Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same |
| US5578527A (en) * | 1995-06-23 | 1996-11-26 | Industrial Technology Research Institute | Connection construction and method of manufacturing the same |
| CN1212786A (en) * | 1996-03-06 | 1999-03-31 | 松下电器产业株式会社 | Semiconductor device and process for producing the same |
| CN1266283A (en) * | 1999-03-08 | 2000-09-13 | 精工爱普生株式会社 | Semiconductor device, instllation structure for smeiconductor device, liquid crystal device and electronic device |
| US6558979B2 (en) * | 1996-05-21 | 2003-05-06 | Micron Technology, Inc. | Use of palladium in IC manufacturing with conductive polymer bump |
-
2003
- 2003-09-24 CN CNB031575595A patent/CN100356559C/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5508228A (en) * | 1994-02-14 | 1996-04-16 | Microelectronics And Computer Technology Corporation | Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same |
| US5578527A (en) * | 1995-06-23 | 1996-11-26 | Industrial Technology Research Institute | Connection construction and method of manufacturing the same |
| CN1212786A (en) * | 1996-03-06 | 1999-03-31 | 松下电器产业株式会社 | Semiconductor device and process for producing the same |
| US6558979B2 (en) * | 1996-05-21 | 2003-05-06 | Micron Technology, Inc. | Use of palladium in IC manufacturing with conductive polymer bump |
| CN1266283A (en) * | 1999-03-08 | 2000-09-13 | 精工爱普生株式会社 | Semiconductor device, instllation structure for smeiconductor device, liquid crystal device and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1601737A (en) | 2005-03-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7268436B2 (en) | Electronic device with cavity and a method for producing the same | |
| CN100533712C (en) | Optoelectronic device chip and method for making same | |
| KR100669273B1 (en) | Mounting method of surface acoustic wave element and surface acoustic wave device having resin-sealed surface acoustic wave element | |
| US5989942A (en) | Method for fabricating semiconductor device | |
| US7423348B2 (en) | Chip structure and chip package structure | |
| KR19990028493A (en) | Electronic component and method of production thereof | |
| US6467139B1 (en) | Mounting structure and mounting method for surface acoustic wave element | |
| KR20020009087A (en) | Semiconductor package and package method | |
| CN101241921A (en) | Optical device and method for manufacturing optical device, and camera module and endoscope module | |
| CN102540646A (en) | Camera module and method for fabricating the same | |
| CN110262701A (en) | A kind of display panel and display device | |
| WO2014061204A1 (en) | Semiconductor device and method for manufacturing same | |
| US6815263B2 (en) | Component assembly and method for producing the same | |
| CN100356559C (en) | Crystal coated packing structure and its mfg method | |
| CN1317761C (en) | Flip chip packaging joint structure and method for manufacturing same | |
| CN1309067C (en) | Elastic lug structure and its mfg method | |
| WO2018093137A1 (en) | Surface acoustic wave element package and manufacturing method thereof | |
| CN100483703C (en) | Piled semiconductor packing structure and its production | |
| CN109326620A (en) | A kind of embedded packaging structure and production method of image sensing chip | |
| JPH04137663A (en) | Solid-state image sensor | |
| US5605863A (en) | Device packaging using heat spreaders and assisted deposition of wire bonds | |
| JPH09246318A (en) | Semiconductor device and manufacture thereof | |
| JP2841721B2 (en) | Structure of protruding electrode bump and manufacturing method thereof | |
| CN100521171C (en) | Package bonding structure of element | |
| JP3443196B2 (en) | Semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20071219 |