CN1317761C - Flip chip packaging joint structure and method for manufacturing same - Google Patents
Flip chip packaging joint structure and method for manufacturing same Download PDFInfo
- Publication number
- CN1317761C CN1317761C CNB031370918A CN03137091A CN1317761C CN 1317761 C CN1317761 C CN 1317761C CN B031370918 A CNB031370918 A CN B031370918A CN 03137091 A CN03137091 A CN 03137091A CN 1317761 C CN1317761 C CN 1317761C
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- CN
- China
- Prior art keywords
- substrate
- dielectric film
- conductive
- chip package
- joint sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
The present invention relates to a flip chip encapsulation joint structure and a manufacture method thereof. The flip chip encapsulation joint structure comprises a substrate, an assembly and anisotropic conductive adhesion agent, wherein a plurality of joint pads are formed on the surface of the substrate and are used as conductive lines of the substrate; a plurality of conductive convex blocks are formed on the surface of the assembly, and the lateral surface of each conductive convex block has an insulation film in order to isolate the lateral electric conduction of the conductive convex block; the conductive convex blocks press and close the joint pads in order to be electrically connected with the substrate and the assembly; the anisotropic conductive adhesion agent comprises a plurality of conductive particles, and the anisotropic conductive adhesion agent is spread on a joint region between the substrate and the assembly in order to be joint with the substrate and the assembly. The present invention can prevent a short-circuit phenomenon generated by the collection of the conductive particles of the conductive adhesion agent, and the present invention is applied to flip chip encapsulation of an assembly with thin-wire width and fine spacing using the conductive adhesion agent.
Description
Technical field
The present invention relates to a kind of chip package connected structure and manufacture method thereof, particularly a kind of chip package connected structure and manufacture method thereof of using anisotropy conduction solid.
Background technology
Be accompanied by the development trend of electronic product towards light, thin, short, little, high speed and high mechanization, and making the semiconductor subassembly encapsulation technology improve constantly for the requirement that increases the assembly reliability, engages density and reduce the size of components aspect, therefore traditional routing engages (wire bonding) brilliant (flip-chip upside-down mounting) technology that encapsulates that be covered gradually and replaces.
The chip package technology is with the composition surface formation arrays of solder balls (array of solderball) of chip and substrate or conductive projection (bump) is to replace the employed lead frame of known encapsulation technology (leadframe).Reach circuit turn-on by arrays of solder balls between the composition surface of direct pressing chip and substrate (array of solderball) or conductive projection, can reduce the electric signal transmission range between chip and substrate, be applicable to the encapsulation of high-speed assembly.Known crystal coated encapsulation method, the surface that lies in chip and substrate forms conductive projection connected structures such as (bump), then at substrate surface coating solid; Conductive projection with chip and substrate surface passes through the contraposition pressing to finish composite packing structure again.When using solid to be engaged between chip and substrate, because both have serious thermal expansion coefficient difference, when temperature changed, the influence of thermal stress made the conductive projection contact of chip and substrate produce distortion easily.
For thermal expansion coefficient difference that reduces solid, substrate and chip chamber and the intensity that increases contact, can in the glue material, sneak into suitable particle to adjust the thermal expansion coefficient difference of solid, and can in solid, add the conducting particles of debita spissitudo, with form the anisotropic conductive solid (AnisotropicConductive Film, ACF).But under the situation of very fine pitch, the conducting particles of anisotropic conductive solid is gathered in the side of contact easily and produces adjacent contact situation of short circuit, so its applicable live width of institute and pitch-limited.
Summary of the invention
Method forms dielectric film in the contact side of chip and substrate, assemble the short circuit phenomenon that produces to block between the contact because of the conducting particles of conduction solid, and this chip package connected structure can be applied to the assembly chip package of the wide and thin space of fine rule.
The present invention discloses a kind of chip package connected structure and manufacture method thereof of using the anisotropic conductive solid, be dielectric film the electrically conducting of utilizing the contact side of assembly and substrate with isolated its side direction, its modular construction is to be coated on the conducting particles that the contact side directly intercepts the conductivity solid with dielectric film, prevents to assemble the short circuit phenomenon that produces because of conducting particles between contact.Its chip package connected structure is formed by substrate, assembly and anisotropic conductive solid, and wherein substrate surface forms several joint sheets with the conducting wire as substrate; Assembly surface forms several conductive projections, and the conductive projection side is to form a dielectric film, and the dielectric film that adjacent two conductive projections are had does not link to each other, and its conductive projection is pressed on the joint sheet of substrate, to form electrically conducting of substrate and assembly; And include the conductivity solid of several conducting particless, be to be filled in the engaging zones of substrate and assembly to electrically connect substrate and assembly.
In addition, the present invention also comprises the manufacture method of chip package connected structure, is to form several conductive projections and joint sheet respectively on the surface of above-mentioned assembly and substrate; Form dielectric film in each conductive projection side; Simultaneously in substrate surface coating anisotropic conductive solid; Again with pressing behind several joint sheets on several conduction conductive projection align substrates surfaces of assembly surface, and solidify the anisotropic conductive solid.Also may be piled up in owing to conducting particles between the joint sheet of substrate and cause short circuit, so form a dielectric film in the joint sheet side of substrate.
Description of drawings
Fig. 1 is the structural representation of first embodiment of the invention;
Fig. 2 is the continuous distribution schematic diagram of dielectric film of the present invention;
Fig. 3 is the continuous distribution schematic diagram of dielectric film of the present invention;
Fig. 4 to Fig. 6 is the making schematic flow sheet of dielectric film;
Fig. 7 to Fig. 9 is the making schematic flow sheet of dielectric film;
Figure 10 is the making flow chart of first embodiment of the invention; And
Figure 11 is the structural representation of second embodiment of the invention.
Reference numeral wherein
100 chips
110 conductive projections
111 dielectric films
111 dielectric films
120 conductivity solids
130 light shields
140 abrasive wheels
121 conducting particless
200 substrates
210 joint sheets
211 dielectric films
The anisotropic conductive solid that step 340 will contain conducting particles is covered on the substrate
Embodiment
For making purpose of the present invention, structural feature and function thereof are had further understanding, conjunction with figs. is described in detail as follows:
Crystalline substance (flip chip, flip-chip) package bonding structure and the manufacture method thereof covered disclosed according to the present invention is to use the anisotropic conductive solid with conjugative component and substrate, the short circuit problem that is easy to generate when its spacing dwindles for solving.The conducting particles that contains suitable concentration in the anisotropic conductive solid, high more its conduction property of concentration is good more, relatively also produce short circuit between the contact because of conducting particles accumulates in easily, it can be applicable to engaging of various semiconductor packages and package assembly, particularly chip and substrate.
Preferred embodiment of the present invention, formed by substrate, chip and anisotropic conductive solid, please refer to Fig. 1, it is the structural representation of first embodiment of the invention, it comprises: a chip 100, its surface has several conductive projections 110, and the side of its conductive projection 110 is to have dielectric film 111; One substrate 200, its surface have several joint sheets 210; And an anisotropic conductive solid 120, be for containing the macromolecular material of conducting particles 121.Chip 100 and substrate 200 are to engage in aspectant mode several conductive projections 110 individually are pressed on several joint sheets 210 and form and electrically conduct.Wherein, characteristic point of the present invention is the side that is the contact of chip and substrate, as conductive projection or joint sheet, forms dielectric film.According to the difference of manufacture process or application, the distribution form of its dielectric film can cooperate adjustment, as only coating around the contact or coating the entire chip surface and only expose joint, promptly is filled between each conductive projection or the gap between the joint sheet.Please refer to Fig. 2 and Fig. 3, it is a dielectric film distribution schematic diagram of the present invention.
As shown in Figure 2, dielectric film 111 is only to be formed at around the conductive projection 110 on chip 100 surfaces.
As shown in Figure 3, dielectric film 111 is the entire engagement surface that are formed at chip 100, promptly is filled in the gap between each conductive projection 110, only exposes conductive projection 110 conductive bond faces.
The dielectric film of chip package connected structure can be made by several different methods, please refer to Fig. 4 to Fig. 6, and it is the making schematic flow sheet of dielectric film, is to cooperate photolithographic techniques to make dielectric film.
As shown in Figure 4, provide a chip 100, form several conductive projections 110 on its surface, and in chip 100 surface coated photoresists as dielectric film 111, and cover conductive projection 110 fully.
As shown in Figure 5, use the zone of the conductive projection 110 conductive bond faces on light shield 130 exposure chips 100 surfaces.
As shown in Figure 6, the pattern of development photoresist makes it form dielectric film 111 in conductive projection 110 sides, and exposes the conductive bond face of conductive projection 110.
In addition, also can use plated film after the mechanical lapping mode form dielectric film, please refer to Fig. 7 to Fig. 9, it is the making schematic flow sheet of dielectric film.
As shown in Figure 7, provide a chip 100, form several conductive projections 110 on its surface, and in chip surface sputter semiconducting insulation material with as dielectric film 112, and cover conductive projection 110 fully.
As shown in Figure 8, impose cmp with 140 pairs of conductive projection 110 surfaces of abrasive wheel, until the conductive bond face that exposes conductive projection 110.
As shown in Figure 9, behind the semiconducting insulation layer of the conductive bond face of removal conductive projection 110, chip 100 surfaces promptly form dielectric film 111 that is covered in conductive projection 110 sides and the conductive bond face that exposes conductive projection 110.
The difference of coordinated insulation film manufacturing process, its material and its dispensing area in order to the dielectric film of covering conductive projection side can be done various adjustment, cooperates different manufacturing process, and dielectric film can be selected photoresist or insulating material.Chip package connected structure disclosed in this invention and manufacture method thereof can be used for any semiconductor assembling and use, and be particularly suitable for the chip for driving of LCD (LCD) and engaging of glass substrate or soft substrate plate.
Please refer to Figure 10, it is the making flow chart of first embodiment of the invention, at first, provides a chip, forms several conductive projections (step 310) on its surface; Secondly, provide a substrate, form several joint sheets (step 320) in its surface; Form dielectric film (step 330) in chip surface, dielectric film is coated with conductive projection side and the conductive bond face that exposes conductive projection; The anisotropic conductive solid that will contain conducting particles again is covered in (step 340) on the substrate; The location of aiming at via chip and substrate makes conductive projection aim at joint sheet, and contraposition pressing chip and substrate and curing conductive solid then are with formation chip package connected structure (step 350).Above-mentioned substrate can be selected organic group plate, ceramic substrate, glass substrate, silicon substrate or GaAs substrate or the like.Its anisotropic conductive solid also can select the polymer-based solid of polymer-based solid, photocuring of hot curing or other to follow material, and compounding ingredient solidifies in modes such as heating, exposure or microwaves.
Also may be piled up in owing to conducting particles between the joint sheet of substrate and cause short circuit, the joint sheet side of substrate also can form a dielectric film, also be included in the step of substrate formation dielectric film in making process step of the present invention, dielectric film is the conductive bond face that coats the joint sheet side and expose joint sheet.Please refer to Figure 11, it is the structural representation of second embodiment of the invention.Chip 100 and substrate 200 are to engage in aspectant mode to make several conductive projections 110 individually be pressed on several joint sheets 210 and form and electrically conduct.In the contact side of chip and substrate, comprise conductive projection 110 and joint sheet 210, all form dielectric film 111,211 and prevent to produce the short circuit phenomenon that gathering produces because of the conducting particles 121 of anisotropic conductive solid 120.
Though preferred embodiment of the present invention openly as mentioned above; right its is not in order to qualification the present invention, any those of ordinary skills, without departing from the spirit and scope of the present invention; when doing some changes and modification, therefore scope of patent protection of the present invention is as the criterion with claim.
Claims (18)
1. a chip package connected structure is characterized in that, includes:
One substrate, its surface forms several joint sheets with the conducting wire as this substrate;
One assembly, its surface forms several conductive projections, and this conductive projection side is to have a dielectric film to completely cut off electrically conducting of its side direction, and the dielectric film that adjacent two conductive projections are had does not link to each other, these several conductive projections are pressed on this several joint sheets, to electrically connect this substrate and this assembly; And
One anisotropic conductive solid includes several conducting particless, and this anisotropic conductive solid is to coat the engaging zones of this substrate and this assembly to follow this substrate and this assembly.
2. chip package connected structure as claimed in claim 1 is characterized in that, the material of this dielectric film be for photoresist and insulating material one of them.
3. chip package connected structure as claimed in claim 1 is characterized in that, this dielectric film is to be filled in gap between this conductive projection to cover this conductive projection side.
4. chip package connected structure as claimed in claim 1 is characterized in that, this joint sheet side is to cover a joint sheet dielectric film.
5. chip package connected structure as claimed in claim 4 is characterized in that, the material of this joint sheet dielectric film be for photoresist and insulating material one of them.
6. chip package connected structure as claimed in claim 4 is characterized in that, this joint sheet dielectric film is to be filled in gap between this joint sheet to cover this joint sheet side.
7. chip package connected structure as claimed in claim 1 is characterized in that, this assembly is to be a LCD device drive chip.
8. chip package connected structure as claimed in claim 1 is characterized in that, this substrate be selected from group that organic substrate, ceramic substrate, glass substrate, silicon substrate and GaAs substrate formed one of them.
9. chip package connected structure as claimed in claim 1 is characterized in that, this anisotropic conductive solid be selected from thermally curable polymer base solid and the polymer-based solid of photocuring one of them.
10. the manufacture method of a chip package connected structure is characterized in that, step includes:
One assembly is provided, forms several conductive projections in its surface;
One substrate is provided, forms several joint sheets in its surface;
Form a dielectric film in this conductive projection side;
Be coated with an anisotropic conductive solid in this substrate surface;
Make this conductive projection aim at this joint sheet that is pressed on this substrate surface; And
Solidify this anisotropic conductive solid to engage this assembly and this substrate.
11. the manufacture method of chip package connected structure as claimed in claim 10 is characterized in that, should form the step of dielectric film in this conductive projection side, is this dielectric film is filled in gap between this conductive projection, to cover the side of this conductive projection.
12. the manufacture method of chip package connected structure as claimed in claim 10 is characterized in that, should form the step of a dielectric film in this conductive projection side, is to form this dielectric film with the light lithography method in this conductive projection side.
13. the manufacture method of chip package connected structure as claimed in claim 10, it is characterized in that, should form the step of a dielectric film in this conductive projection side, be in the assembly surface depositing insulating layer, impose cmp again and remove the insulating barrier on this conductive projection surface, be covered in this dielectric film of this conductive projection side with formation.
14. the manufacture method of chip package connected structure as claimed in claim 10 is characterized in that, also is included in the step that this substrate forms a joint sheet dielectric film.
15. the manufacture method of chip package connected structure as claimed in claim 14 is characterized in that, should be in this joint sheet side form the step of a joint sheet dielectric film, is this dielectric film is filled in gap between this joint sheet, to cover the side of this joint sheet.
16. the manufacture method of chip package connected structure as claimed in claim 14 is characterized in that, should form the step of a joint sheet dielectric film in this joint sheet side, is to form this joint sheet dielectric film with the light lithography method in this joint sheet side.
17. the manufacture method of chip package connected structure as claimed in claim 14, it is characterized in that, should form the step of a joint sheet dielectric film in this joint sheet side, in this substrate surface depositing insulating layer, impose cmp again and remove the insulating barrier of this gasket surface, be covered in this joint sheet dielectric film of this joint sheet side with formation.
18. the manufacture method of chip package connected structure as claimed in claim 14 is characterized in that, this solidifies this anisotropic conductive solid to engage the step of this assembly and this substrate, be selected from heating, exposure and microwave method one of them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031370918A CN1317761C (en) | 2003-06-18 | 2003-06-18 | Flip chip packaging joint structure and method for manufacturing same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031370918A CN1317761C (en) | 2003-06-18 | 2003-06-18 | Flip chip packaging joint structure and method for manufacturing same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1567582A CN1567582A (en) | 2005-01-19 |
| CN1317761C true CN1317761C (en) | 2007-05-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB031370918A Expired - Fee Related CN1317761C (en) | 2003-06-18 | 2003-06-18 | Flip chip packaging joint structure and method for manufacturing same |
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| CN (1) | CN1317761C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110085558A (en) * | 2018-01-26 | 2019-08-02 | 力成科技股份有限公司 | Encapulant composition, semiconductor packages and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100477140C (en) * | 2006-05-19 | 2009-04-08 | 台湾薄膜电晶体液晶显示器产业协会 | Packing component of semiconductor and preparing method thereof |
| KR100891517B1 (en) * | 2007-06-18 | 2009-04-06 | 주식회사 하이닉스반도체 | Flip chip package and method of manufacturing the same |
| CN101216619B (en) * | 2008-01-10 | 2010-09-22 | 友达光电股份有限公司 | Planar display and method of manufacture and photoelectric device and process for production thereof |
| CN101256998B (en) * | 2008-04-10 | 2010-06-16 | 日月光半导体制造股份有限公司 | Semiconductor device using anisotropic conductive adhesive layer and manufacturing method thereof |
| JP6715052B2 (en) * | 2016-03-25 | 2020-07-01 | デクセリアルズ株式会社 | Method for manufacturing connection structure |
| CN106653749A (en) * | 2017-01-04 | 2017-05-10 | 昆山工研院新型平板显示技术中心有限公司 | Display module and preparation method thereof |
| CN108831872A (en) * | 2018-06-08 | 2018-11-16 | 云谷（固安）科技有限公司 | bonding structure and bonding method |
| CN109257873B (en) * | 2018-11-13 | 2021-04-16 | 珠海景旺柔性电路有限公司 | Forming process of wireless charging circuit board and wireless charging circuit board |
| CN110930879B (en) * | 2019-11-25 | 2020-11-10 | 武汉华星光电半导体显示技术有限公司 | Display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0864636A (en) * | 1994-08-25 | 1996-03-08 | Seiko Epson Corp | Electronic device assembly |
| JP2000124249A (en) * | 1998-10-16 | 2000-04-28 | Seiko Epson Corp | Semiconductor device, semiconductor mounting substrate, liq. crystal display and electronic equipment using the device |
| CN1270417A (en) * | 1999-04-14 | 2000-10-18 | 夏普公司 | Semiconductor device and manufacture thereof |
| US6489180B1 (en) * | 2000-09-28 | 2002-12-03 | Siliconware Precision Industries Co., Ltd. | Flip-chip packaging process utilizing no-flow underfill technique |
-
2003
- 2003-06-18 CN CNB031370918A patent/CN1317761C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0864636A (en) * | 1994-08-25 | 1996-03-08 | Seiko Epson Corp | Electronic device assembly |
| JP2000124249A (en) * | 1998-10-16 | 2000-04-28 | Seiko Epson Corp | Semiconductor device, semiconductor mounting substrate, liq. crystal display and electronic equipment using the device |
| CN1270417A (en) * | 1999-04-14 | 2000-10-18 | 夏普公司 | Semiconductor device and manufacture thereof |
| US6489180B1 (en) * | 2000-09-28 | 2002-12-03 | Siliconware Precision Industries Co., Ltd. | Flip-chip packaging process utilizing no-flow underfill technique |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110085558A (en) * | 2018-01-26 | 2019-08-02 | 力成科技股份有限公司 | Encapulant composition, semiconductor packages and its manufacturing method |
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| CN1567582A (en) | 2005-01-19 |
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