CN1246900C - Semiconductor device and manufacture method - Google Patents

Semiconductor device and manufacture method Download PDF

Info

Publication number
CN1246900C
CN1246900C CNB001007556A CN00100755A CN1246900C CN 1246900 C CN1246900 C CN 1246900C CN B001007556 A CNB001007556 A CN B001007556A CN 00100755 A CN00100755 A CN 00100755A CN 1246900 C CN1246900 C CN 1246900C
Authority
CN
China
Prior art keywords
expansion
thermal coefficient
sealing film
particle
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB001007556A
Other languages
Chinese (zh)
Other versions
CN1264173A (en
Inventor
桑原治
若林猛
三原一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhao Tan Jing Co ltd
Aoi Electronics Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Publication of CN1264173A publication Critical patent/CN1264173A/en
Application granted granted Critical
Publication of CN1246900C publication Critical patent/CN1246900C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02377—Fan-in arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Measuring Fluid Pressure (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor device includes a semiconductor substrate having bump electrodes and a sealing film formed thereon, the sealing film having laminated layers. The semiconductor device is mounted to another circuit substrate via the bump electrodes. The sealing film interposed between adjacent bump electrodes is prepared by laminating a protective film and each layer of the sealing film on the lower surface of the base film, on the bump electrodes, followed by allowing the bump electrodes to project through the sealing film under pressure and heat. The thickness of the sealing film is smaller than the height of the bump electrode, and thus the bump electrode projects through the sealing film. The stress derived from the difference in thermal expansion coefficient between the semiconductor substrate and the circuit substrate is absorbed by the projecting portion of the bump electrode. In forming the sealing film, particles for lowering the thermal expansion coefficient are dispersed in the sealing film to allow the sealing layers to exhibit a thermal expansion coefficient differing in its thickness direction such that the thermal expansion coefficient in the layer which is close to the semiconductor substrate is close to that of the semiconductor substrate so as to absorb the stress derived from the difference in thermal expansion coefficient between the semiconductor substrate and the sealing film. By absorbing the stress derived from the difference in thermal expansion coefficient between the semiconductor substrate and the circuit substrate and between the semiconductor substrate and the sealing film, a defective connection can be prevented so as to improve the reliability.

Description

Semiconductor device and manufacture method
Technical field
The present invention relates to a kind of semiconductor device and preparation method thereof with lug electrode.
Background technology
Be mounted in some situation of a circuit substrate in that the semiconductor device that the semiconductor device is made up of single semiconductor chip maybe will be called CSP (chip size assembly) is installed, employing is called the mounting technique of inverse bonding system.In such semiconductor device, the lug electrode that is used for for example being connected to another circuit substrate directly be mounted to the semiconductor substrate or be mounted to be inserted with therebetween in the middle of the semiconductor substrate of substrate (insert).
Usually make such semiconductor device by the manufacturing process shown in Figure 11 A and the 11B.Particularly, shown in Figure 11 A, on the semiconductor chip 2 of a silicon chip of a for example wafer state, form a plurality of lug electrodes 3.Then, a diaphragm seal 4 of being made by epoxy resin by formation such as silk screen print method, package method, transfer mo(u)lding methods is so that the thickness of diaphragm seal 4 what greater than the height of lug electrode 3.Therefore, under this state, the upper surface of lug electrode 3 is coated with diaphragm seal 4.Then, the upper area of diaphragm seal 4 is suitably polished so that the upper surface of lug electrode 3 is exposed to the outside, shown in Figure 11 B.After this polishing step, this silicon wafer is divided into semiconductor chip separately so that obtain to be provided with the semiconductor device of lug electrode in a cutting step (not shown).
On the lug electrode of the semiconductor device 1 for preparing like this, form weld flange and these weld flanges are mounted to another circuit substrate by the inverse bonding method connection welding.Figure 12 illustration the mounting structure of such preparation.This semiconductor chip 1 comprises a silicon chip 2 flat and rectangle, and is formed for being connected to a plurality of connection welding 5 of external device (ED) on the lower surface of this silicon chip 2.On the whole lower surface of connection welding except the middle body of connection welding 55 and silicon chip 2, form a dielectric film 6 so that the middle body of this connection welding 5 is exposed to the outside by the opening portion that forms in this dielectric film 6.One distribution substrate metal level 8 is formed to extend to the lower surface of dielectric film 6 from the lower surface that exposes of connection welding 5.In the case, this distribution substrate metal level 8 divide 8a, be positioned at the connection welding part 8b in the predetermined portions of lower surface of dielectric film 6 and be formed on this coupling part by a junction below connection welding 5 and this connection welding between tractive wiring 8c.On the lower surface of connection welding part 8b, form by copper.The lug electrode 3 that gold etc. are formed.And, on the lower surface of wiring except lug electrode 38 and dielectric film 6, form an epoxy resin.On the lower surface of lug electrode 3, form weld flange 9.The weld flange 9 that should be noted that semiconductor device 1 is soldered to the connection welding 11 that forms on the upper surface of a circuit substrate 10 by inverse bonding, this circuit substrate 10 for example is made up of glass epoxy, so that this semiconductor device 1 is mounted to circuit substrate 10.
The glass epoxy that should be noted that the silicon that constitutes silicon chip 2, the sealing resin that constitutes diaphragm seal 4 and forming circuit substrate 10 is different mutually on thermal coefficient of expansion.Particularly, the thermal coefficient of expansion of silicon is 2 to 3ppm/ ℃, and the thermal coefficient of expansion of sealing resin is 10 to 15ppm/ ℃, and the thermal coefficient of expansion of glass epoxy is about 15ppm/ ℃.Should be noted that diaphragm seal 4 and circuit substrate 10 are approaching mutually on thermal coefficient of expansion.On the other hand, the difference of the thermal coefficient of expansion between diaphragm seal 4 and the silicon chip 2 is relatively large.As a result, as shown in figure 12, be soldered to through weld flange 9 under the situation of circuit substrate 10,, between silicon chip 2 and diaphragm seal 4, generate big relatively stress by the difference derivation of thermal coefficient of expansion by variation of temperature at semiconductor device 1.What it should be noted that in this connection is the height that the thickness of dielectric film 4 equals lug electrode 3.Draw lug electrode 3 thus and can not be deformed so that be absorbed between silicon chip 2 and the diaphragm seal 4 stress that generates, cause the crack occurring in the welding portion between lug electrode 3 and weld flange 9 or in the welding portion between weld flange 9 and connection welding 11.The appearance in this crack has brought the problem that is difficult to guarantee gratifying welding.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor device, be included in the lug electrode and the diaphragm seal that form on the semiconductor substrate, this semiconductor device through lug electrode be mounted to another circuit substrate and have be used to be absorbed between this semiconductor chip and the circuit substrate and the stress that difference derived of the thermal coefficient of expansion between semiconductor chip and the diaphragm seal so that suppress a structure and a kind of method of making this particular semiconductor device that defective welding occurs.
For achieving the above object, first semiconductor device of the present invention is characterised in that and forms a diaphragm seal between the adjacent lug electrode on the semiconductor chip, the sealing film is formed by having the two-layer of suitably being controlled at least of thermal coefficient of expansion, and the thickness of each layer of sealing film is less than the height of lug electrode.When the thickness of whole diaphragm seal was made height less than lug electrode, lug electrode stretched out from diaphragm seal, and the extension of lug electrode is absorbed in the stress that difference derived of the thermal coefficient of expansion between this semiconductor chip and the circuit substrate.A kind of method of making the semiconductor device of this ad hoc structure includes step: form a stack membrane, be made up of a diaphragm on the lower surface that is formed on a basement membrane and a diaphragm seal that is formed on this diaphragm, the sealing film is made up of multilayer; This stack membrane that deposition forms like this on lug electrode, then this stack membrane of pressurized, heated is so that lug electrode extends through diaphragm seal; And peel off this basement membrane and diaphragm, thereby prevent the lug electrode fracture or damage so that diaphragm is carried out the function of buffer unit.
For achieving the above object, first semiconductor device of the present invention is characterised in that in the thermal coefficient of expansion Be Controlled of the diaphragm seal that forms between the adjacent lug electrode on the semiconductor chip so that on its thickness direction difference is being arranged so that the thermal coefficient of expansion of the diaphragm seal on this side of semiconductor chip approaches the thermal coefficient of expansion that the thermal coefficient of expansion of the diaphragm seal on this side of the thermal coefficient of expansion of semiconductor chip and circuit substrate approaches circuit substrate.This specific formation allows to be absorbed in the stress that difference derived of the thermal coefficient of expansion between this semiconductor chip and the diaphragm seal.A kind of method of making the semiconductor device of this ad hoc structure, include step: by solidifying to form the particle that is mixed for reducing thermal coefficient of expansion in the diaphragm seal, the volume ratio of these particles is suitably being allowed the sealing film to present different thermal coefficient of expansion mutually on its thickness direction after the control on the thickness direction of sealing film.
Other purposes of the present invention and advantage will be described in the following description, and be conspicuous partly, maybe can understand by putting into practice the present invention.Objects and advantages of the present invention can be implemented and obtain by means and the combination that hereinafter specifically provides.
Description of drawings
Accompanying drawing combined at this and that constitute the part of specification has provided the preferred embodiments of the present invention.And together with above general introduction and below the detailed description that provides, explain principle of the present invention.
Fig. 1 is the cross sectional view of a mounting structure, and wherein the semiconductor device according to the first embodiment of the present invention is mounted to another circuit substrate through lug electrode;
Fig. 2 be illustrate according to having of the first embodiment of the present invention be mounted to its lug electrode semiconductor chip and in manufacturing process, form the cross sectional view of the step of a stack membrane;
Fig. 3 be illustrate according to the first embodiment of the present invention in manufacturing process on a platform location semiconductor device and on lug electrode, deposit the cross sectional view of the step of a stack membrane in the mode of aiming at;
Fig. 4 be illustrate according to the first embodiment of the present invention in manufacturing process between a heated sheet and this platform heating and pressurizing allow lug electrode to extend through the cross sectional view of the step of sealing film with diaphragm seal one;
Fig. 5 is the cross sectional view that illustrates according to the step of peeling off a basement membrane and a diaphragm in manufacturing process of the first embodiment of the present invention;
Fig. 6 illustrates to replace the cross sectional view that hot pressurization steps is used the step of a pressurized, heated roller of falling among Fig. 4 according to the first embodiment of the present invention in manufacturing process;
Fig. 7 is the cross sectional view of a mounting structure, and wherein semiconductor device according to a second embodiment of the present invention is mounted to another circuit substrate through lug electrode;
Fig. 8 A to 8E is the cross sectional view that the venue illustrates a manufacturing process according to a second embodiment of the present invention;
Fig. 9 is that heat pressurization one diaphragm seal that falls between a heated sheet and this platform in manufacturing process that illustrates according to a second embodiment of the present invention extends through the cross sectional view of the step of sealing film to allow lug electrode;
Figure 10 is the cross sectional view of the main points part of a mounting structure, and wherein semiconductor device according to a second embodiment of the present invention is mounted to another circuit substrate through lug electrode;
Figure 11 A and 11B are the cross sectional view that the venue illustrates the step of the lug electrode that forms conventional structure;
Figure 12 is the cross sectional view of a mounting structure, and the semiconductor device that wherein has the lug electrode of conventional structure is mounted to another circuit substrate through lug electrode.
Embodiment
Hereinafter with reference to accompanying drawing semiconductor device of the present invention and preparation method thereof is elaborated.
Particularly, Fig. 1 is the cross sectional view of a mounting structure, and wherein the semiconductor device according to the first embodiment of the present invention is mounted to another circuit substrate through lug electrode.In this embodiment, semiconductor device 20 is included in a plurality of lug electrodes 22 that form on the semiconductor substrate 21.On the other hand, form a plurality of connection welding 32 in the predetermined portions on the upper surface of circuit substrate 31.As shown in the figure, the projecting edge of lug electrode 22 partly is soldered to the weld flange 33 that forms in advance so that allow semiconductor device 20 to be installed on the circuit substrate 31 in connection welding 32.Should be noted that and form diaphragm seal 23,24 in the zone between two adjacent lug electrodes 22 of semiconductor device 20.Each diaphragm seal 23 and 24 is formed by for example resin of epoxy series plastics, biphenyl series plastics, phenolic resins, silicone resin or mylar.Should be noted that and in this resin, be scattered with for example particle that is used to reduce thermal coefficient of expansion of silica dioxide granule.In the case, at the dispersion volume of the particle that is used for reducing thermal coefficient of expansion, diaphragm seal 23 and 24 is made mutual different and therefore present different characteristics.Particularly, the thermal coefficient of expansion of lower seal film 24 is made the thermal coefficient of expansion less than top seal film 23.As a result, the thermal coefficient of expansion of lower seal film 24 approaches the thermal coefficient of expansion of silicon chip 21.Similarly, the thermal coefficient of expansion of top seal film 23 approaches the thermal coefficient of expansion of lug electrode 22.By the way, may only in lower seal film 24, scatter the particle that is used to reduce thermal coefficient of expansion.In other words, may only form top seal film 23 with resin.It should further be appreciated that the height of the gross thickness of the diaphragm seal 23 that is given these concrete properties and 24 less than lug electrode 22.Nature, lug electrode 22 is outstanding by diaphragm seal 23,24, and this ledge allows lug electrode 22 to be easy to rotation.As a result, after semiconductor device 20 is mounted to circuit substrate 31, in the temperature cycling test that provides, can absorb between silicon chips 21 and the circuit substrate 31 the stress that difference derived by lug electrode 22 by thermal coefficient of expansion.It should further be appreciated that, because the thermal coefficient of expansion of lower seal film 24 approaches the thermal coefficient of expansion that the thermal coefficient of expansion of the thermal coefficient of expansion of silicon chip 21 and top seal film 23 approaches lug electrode 22, may reduce between lower seal film 24 and the silicon chip 12 the stress that difference derived by thermal coefficient of expansion.And lug electrode 22 is easy to follow the mobile of top seal film 23 so that suppress the appearance of defective.
Fig. 2 to 5 is used for the cross sectional view according to the manufacturing process of the semiconductor device of the first embodiment of the present invention shown in the construction drawing 1 for expression.
In first step, be formed with preparation one silicon chip 21 in the wafer state of a plurality of lug electrodes 22 thereon and by a basement membrane 25, be layered in a diaphragm 26 on the lower surface of basement membrane 25, be layered in the top seal film 23 on the lower surface of diaphragm 26 and be layered in the stacked film 27 that the lower seal film 24 on the lower surface of top seal film 23 constitutes.Basement membrane 25 is formed by the engineering plastic materials of for example polyimides or PET (polyethylene is to stupid dicarboxylic acid esters).Diaphragm 26 is formed by urethane resin.And each diaphragm seal 23 and 24 is formed by for example resin of epoxy series plastics, biphenyl series plastics, phenolic resins, silicone resin or mylar, and is as discussed previously.It should be noted that the particle that is used for reducing thermal coefficient of expansion of silica dioxide granule for example is dispersed in this resin.In the case, diaphragm seal 23 and 24 is made to be used to reduce on the dispersion volume of particle of thermal coefficient of expansion different mutually at this, and so presents different characteristics.And diaphragm seal 23 and 24 gross thickness are made half less than the height of lug electrode 22.When for example height of lug electrode 22 was about 150 μ m, diaphragm seal 23 and 24 gross thickness were set at about 50 to 70 μ m.The thickness of diaphragm 26 be determined with the gross thickness that allows diaphragm 26 and diaphragm seal 23,24 what greater than the height of lug electrode 22.By on the lower surface of basement membrane 25, stacking diaphragm 26, then stacking lower seal film 24 on the lower surface of diaphragm 26 and then on the lower surface of lower seal film 24, stacking top seal film 23 and diaphragm 26 and diaphragm seal 23,24 are overlayed on the basement membrane 25.Replacedly, available flowable materials applies the lower surface of basement membrane 25, and then the material of cured coated forms diaphragm 26 and diaphragm seal 23,24 in the mode of lamination.
In next step, as shown in Figure 3, depositing silicon substrate 21 on the part of an expectation of one 41.Then, on the upper surface of lug electrode 22, stack membrane 27 is installed so that lower seal film 24 directly contacts with the upper surface of lug electrode 22 in the mode of aiming at.
Then, stack membrane 27 is pressurizeed on this side of basement membrane 25 by heating-pressure-producing part of forming by a heating plate 42 and a heat-resistant rubber slab 43 that is installed in the lower surface of heating plate 42, as shown in Figure 4.At the same time, platform 41 and heating plate 42 are heated so that about 150 ℃ heating-up temperature to be provided.As a result, diaphragm 26 and diaphragm seal 23,24 are softened to allow lug electrode 22 to give prominence to and pass through lower seal film 24 and top seal films 23, and are therefore covered in diaphragm 26.As discussed previously, the gross thickness of diaphragm 26 and diaphragm seal 23,24 is greater than the height of lug electrode 22.The upper surface that can draw lug electrode 22 can not extend to arrive the lower surface of basement membrane 25.And diaphragm 26 plays the effect of buffer unit, and lug electrode 22 can not ruptured or damage as a result.And the repulsive force of diaphragm 26 allows diaphragm seal 23,24 must be incorporated in to the upper surface of silicon chip 21.
In next step, heating plate 42, heat-resistant rubber slab 43 and platform 41 are removed so that peel off basement membrane 25 and diaphragm 26.As a result, the first half of lug electrode 22 is outstanding from top seal film 23 basically, as shown in Figure 5.In the case, basement membrane 25 and diaphragm 26 can be separated ground or side by side peel off.If heating is suitably applied, these films 25 and 26 can easily be peeled off, no matter these films can be separated ground or side by side peel off.By the way, lug electrode 22 can come Be Controlled by the gross thickness of control diaphragm seal 23 and 24 according to expectation from the outstanding length of last sealant.
Then, diaphragm seal 23 and 24 is cured in a hot curing stove (not shown), then by the cutting process (not shown) this wafer is divided into independent semiconductor chip so that obtain to be provided with the semiconductor device 20 (semiconductor chip) of lug electrode 22 and diaphragm seal 23,24.
In the above-described embodiments, top seal film 23 is formed by the resin of particle that is used to reduce thermal coefficient of expansion that is mixed with silica dioxide granule for example.Replacedly, top seal film 23 can be formed by the epoxy resin of binding agent that is used to reduce modulus of elasticity that for example is mixed with silicone oil for example.In the case, the modulus of elasticity of top seal film 23 is suitably reduced so that allow lug electrode 22 rotation more easily.The medium that replacedly medium and being used to that for example is used for reducing the particle of thermal coefficient of expansion can be reduced modulus of elasticity is added in diaphragm seal 23 together.
And, in the above-described embodiments, may use manufacturing process as shown in Figure 6 to replace the pressurization steps of being heated shown in Fig. 4.In processing shown in Figure 6, the structure shown in Fig. 3, wherein the lower seal film 24 of stack membrane 27 is aligned on the upper surface of a plurality of lug electrodes 22, is inserted between a pair of pressurized, heated roller 44 and 45.In the case, these rollers are rotated with the arrow shown in Fig. 6 so that move this concrete structure in the figure from left to right.Process shown in Fig. 6 makes pressurizes under the condition may be implemented in heating continuously.
In the above-described embodiments, prepare the laminated construction of forming by basement membrane 25, diaphragm 26, top seal film 23 and lower seal film 24 in advance.Replacedly, can deposit continuously on the lug electrode 22 of silicon chip 21 these films 25,26,23 and 24 be used for the heating condition under pressurize.
And in the above-described embodiments, diaphragm 26 is formed by the urethanes series plastics.Replacedly, can form diaphragm 26 by for example stack a diaphragm on the lower surface of basement membrane, described diaphragm is made up of a binding agent (UV curing type binding agent), and its cohesive force to diaphragm seal is reduced under the irradiation of ultraviolet light (UV) immediately.In the case, this basement membrane is by arbitrary composition the among PVC (polyvinyl chloride), EVA (vinyl-vinyl acetate copolymer), the PO (polyolefin) etc.If the lower surface to basement membrane applies fastening processing in advance, promptly use the UV-irradiation basement membrane, do not peel off between basement membrane and the diaphragm, basement membrane and diaphragm can easily be peeled off from diaphragm seal simultaneously as a result.By the way, this basement membrane, diaphragm and two diaphragm seals can form with sheet material separately.
And, in the above-described embodiments, the double-decker that the sealing film is made up of top seal film 23 and lower seal film 24.Yet the sealing film also may be a single layer structure or by three or more multi-layered the composition.Under the situation that adopts single layer structure, diaphragm seal can be formed by previously mentioned arbitrary resin.And, when diaphragm seal for example is a three-decker, can make the thermal coefficient of expansion in intermediate layer and modulus of elasticity centre in lower layer and upper layer.
Fig. 7 is the cross sectional view of the mounting structure of semiconductor device 51 according to a second embodiment of the present invention.As shown in the figure, semiconductor device 51 comprises silicon chip 52 plane and rectangle.Form a plurality of connection welding 53 in the outer peripheral portion on the lower surface of silicon chip 52.Form a dielectric film 54 with the whole lower surface that covers these connection welding except middle body and silicon chip so that outside the middle body of these connection welding 53 is exposed to by the opening 55 that forms in the dielectric film 54.Form a distribution substrate metal level 56 extends to dielectric film 54 with the lower surface from the connection welding 53 that exposes lower surface.Distribution substrate metal level 56 is included in a junction that connection welding 53 belows form and divides 56a, is inserted in tractive wiring 56c between coupling part 56a and the connection welding part 56b at a connection welding part 56b and who forms on the lower surface of dielectric film 54.On the lower surface of each connection welding part 56b, form a plurality of lug electrodes 57 of making by steel, gold etc.Except lug electrode 57, on the lower surface of dielectric film 54, form a diaphragm seal 58.Diaphragm seal 58 is three-deckers, by directly contacting with dielectric film 54 and a bottom diaphragm seal 59 by silica dioxide granule 59b being added epoxy resin 59a preparation, forming by silica dioxide granule 60b being added intermediate seal film 60 that epoxy resin 60a prepares and the top seal film of only being made up of epoxy resin 61. Silica dioxide granule 59a, 60a are used for reducing respectively the thermal coefficient of expansion of bottom and intermediate seal film 59 and 60, and have the identical particle diameter.The silica dioxide granule capacity of epoxy resin 59a is higher than the silica dioxide granule capacity of epoxy resin 60a.As a result, the thermal coefficient of expansion of lower seal film 59 approaches the thermal coefficient of expansion of silicon chip 52, and the thermal coefficient of expansion of intermediate seal film 60 is lower than the thermal coefficient of expansion of epoxy monomer (top seal film 61) and is higher than the thermal coefficient of expansion of lower seal film 59.In other words, the thermal coefficient of expansion of intermediate seal film 60 is in the centre of the thermal coefficient of expansion of the thermal coefficient of expansion of top seal film 61 and lower seal film 59.And because top seal film 61 only is made up of epoxy resin, the thermal coefficient of expansion of top seal film 61 approaches to form the thermal coefficient of expansion of for example glass epoxy resin of distribution substrate 31.On the lower surface of lug electrode 57, form a weld flange 62.Weld flange 62 is connected to the connection welding 32 that forms on the upper surface of distribution substrate 31 so that allow semiconductor device 51 to be mounted to distribution substrate 31 by inverse bonding.
Repeatedly say, in mounting structure shown in Fig. 7, diaphragm seal 58 is three-deckers, by the lower seal film 59 of the thermal coefficient of expansion with the thermal coefficient of expansion that approaches silicon chip 52, have at the intermediate seal film 60 of the thermal coefficient of expansion of the centre of the thermal coefficient of expansion of the thermal coefficient of expansion of top seal film 61 and lower seal film 59 and lower seal film 5 with thermal coefficient of expansion of the thermal coefficient of expansion that approaches silicon chip 52 and form.Can draw, generate between silicon chip 52 and the diaphragm seal 58 by the stress that difference derived of thermal coefficient of expansion even pass through variation of temperature, can reduce between the lower seal film 59 that in three films that constitute sealing film 58, approaches silicon chip 52 most and the silicon chip 52 the stress that difference derived by thermal coefficient of expansion.As a result, occur being inhibited in the crack of coupling part between lug electrode 57 and the weld flange 62 and the connecting portion office between weld flange 62 and connection welding 32.
Fig. 8 A to 8E is the cross sectional view that the venue illustrates the method for making semiconductor device according to a second embodiment of the present invention.
Shown in Fig. 8 A, on the upper surface of the silicon chip 52 of a wafer state, form connection welding 53, then form dielectric film 54 with the upper surface that covers silicon chip 52 and the connection welding except middle body 53 so that in dielectric film 54 formation opening portion 55.Then, form distribution substrate metal level 56 extends to dielectric film 54 with the upper surface of the exposure of connection welding 53 upper surface.And, on the upper surface of distribution substrate metal level 56, form lug electrode 57.
In next step, shown in Fig. 8 B, the upper surface that comprises the dielectric film 54 of epoxy resin 59a coating except lug electrode 57 of a large amount of silica dioxide granule 59b by usefulness such as distribution method, spin coating methods forms lower seal film 59, then solidifies this epoxy resin 59a.Then, shown in Fig. 8 C, the upper surface that comprises the bottom dielectric film 59 of epoxy resin 60a coating except lug electrode 57 of a large amount of silica dioxide granule 60b by usefulness such as distribution method, spin coating methods forms intermediate seal film 60, then solidifies this epoxy resin 60a.And, shown in Fig. 8 D, form top seal film 61 with the upper surface that epoxy resin applies the intermediate seal film 60 except lug electrode 57 by distribution method, spin coating method etc., then solidify this epoxy resin.If apply the upper surface of lug electrode 57 with lower seal film 61 when forming lower seal film 61, the surf zone of top seal film 61 is ground slightly with the upper surface with lug electrode 57 is exposed to the outside.
In next step, as shown in Fig. 8 E, on the upper surface of lug electrode 57, form weld flange 62, then the semiconductor chip 52 of wafer state is cut into independent semiconductor chip so that obtain the semiconductor device 51 shown in Fig. 7 by the cutting process (not shown).
In above-mentioned manufacturing process, can then cut simultaneously and form lower seal film 59, intermediate seal film 60 and top seal film 61 by applying.And in above-mentioned second embodiment, silica dioxide granule 59b and 60b equate on particle diameter.Replacedly, silica dioxide granule 59b can be different mutually on particle diameter with 60b.In this case, the particle diameter of silica dioxide granule 59b can be greater than or less than the particle diameter of silica dioxide granule 60b.Yet, the volume ratio of the silica dioxide granule 59b in the lower seal film 59 need be established in volume ratio greater than the silica dioxide granule 60b in the intermediate seal film 60.And in a second embodiment, diaphragm seal 58 is three-deckers.Yet diaphragm seal 58 can be to comprise four or a sandwich construction of more diaphragm seals.
May adopt the manufacture method of first embodiment to make the semiconductor device 51 of second embodiment.More specifically, as shown in Figure 9, on the lower surface of basement membrane 25, form diaphragm 26 and diaphragm seal 61,60,59.Can then cut these epoxy resin by suitably applying the epoxy resin that comprises silica dioxide granule, or form these diaphragm seals 61,60,59 by the film that the form with sheet stacks these preparations with distribution method, spin coating method etc.Then, silicon chip 52 is aligned on the upper surface of platform 41.And the lower seal film 59 of this stack membrane is aligned on the upper surface of a plurality of lug electrodes 57.In the case, this stack membrane is pressurizeed from this side of basement membrane 25 by heating plate 42 with the heat-resistant rubber slab 43 that is mounted to its lower surface.At the same time, platform 41 and heating plate 42 are heated so that about 150 ℃ heating-up temperature to be provided.As a result, diaphragm 26 and diaphragm seal 61,60,59 are by suitably softening so that lug electrode 57 is outstanding by these diaphragm seals.In the case, by the existence of diaphragm 26, even the gross thickness of these diaphragm seals less than the height of lug electrode 57, the upper surface of lug electrode 57 is prevented from extending the lower surface that arrives basement membrane 25.Can understand and prevent that lug electrode 57 from being ruptured or damage.In next step, heating plate 42, refractory plate 33 and platform 41 are removed so that peel off basement membrane 25 and diaphragm 26, thereby obtain the structure shown in Fig. 8 D.If the upper surface of lug electrode 57 is coated with top seal film 61 or in that to peel off basement membrane 25 and diaphragm 26 back lug electrodes 57 outstanding by the upper surface of top seal film 61, this upper surface is ground slightly with the align upper surface of top seal film 61 of the upper surface with lug electrode 57.Then, on the upper surface of lug electrode 57, form weld flange 62, shown in Fig. 8 E, then the semiconductor chip in the wafer state 52 is cut into independent semiconductor chip by the cutting process (not shown), thereby obtain independent semiconductor device, each structure as shown in Figure 7.
Figure 10 is the main points cross sectional view partly of the semiconductor Unit Installation structure of a third embodiment in accordance with the invention.The common reference number that adopts is represented the same parts of this mounting structure in Fig. 7 and 10, therefore omits some the description in these reference numbers to avoid repetition.A diaphragm seal 79 that comprises in the semiconductor device of the 3rd embodiment is formed by scatter the single resin molding that epoxy resin 71 prepares by three kinds of silica dioxide granules that particle diameter is mutually different 72,73,74.Yet, should be noted that diaphragm seal 79 can be considered to one or four layers structure, form by first sealant 75 of the silica dioxide granule 72 that consists predominantly of the bulky grain diameter, second sealant 76 that consists predominantly of the silica dioxide granule 73 of intermediate particle diameter, the 3rd sealant 77 of silica dioxide granule 74 that consists predominantly of small particle diameters and the 4th sealant 78 that comprises any silica dioxide granule 72,73,74 hardly.These sealants 75,76,77,78 in this order one on another, stack so that first sealant 75 directly contacts with dielectric film 54.It should be noted that the volume ratio of the silica dioxide granule 72,73,74 in the epoxy resin 71 little by little reduces in order so that the big silica dioxide granule 72 that mainly comprises in first sealant 75 is involved with the volume ratio of maximum.Because this concrete structure, even by variation of temperature between silicon chip 52 and diaphragm seal 79 since the gravitation that the difference of thermal coefficient of expansion derives be generated, between first sealant 75 on silicon chip 52 sides and silicon chip 52,, the gravitation that the difference of thermal coefficient of expansion derives improves the reliability of combination, as in a second embodiment because can being reduced.
Semiconductor device 51 how to make the 3rd embodiment will be described below.In first step, for example the structure shown in Fig. 8 B is produced.Then, apply the epoxy resin 71 that is mixed with three kinds of silica dioxide granules 72,73,74 by distribution method, spin coating method etc. at the upper surface of the dielectric film except lug electrode 57 54, the epoxy resin 71 that then rotates this coating is used for eccentrically these silica dioxide granules 72,73,74 being shifted to the surface of the epoxy resin 71 of this coating.The epoxy resin 71 of this coating was made for static one suitable time period.As a result, these silica dioxide granules 72,73,74 are owing to they self weight sinks in the epoxy resin 71.These silica dioxide granules sink to the diameter that the degree of depth depends on these silica dioxide granules.Particularly, the silica dioxide granule 72 with maximum gauge sinks to the most deeply in epoxy resin 71, and the silica dioxide granule 74 with minimum diameter sinks to the most shallowly in epoxy resin 71.Can find out to form a four-layer structure, by first sealant 75 (silica dioxide granule 72 that wherein has the bulky grain diameter mainly is blended in the epoxy resin 71), second sealant 76 (silica dioxide granule 73 that wherein has the intermediate particle diameter mainly is blended in the epoxy resin 71), the 3rd sealant 77 (silica dioxide granule 74 that wherein has small particle diameters mainly is blended in the epoxy resin 71) and the 4th sealant 78 (wherein almost not having silica dioxide granule to be blended in the epoxy resin 71).Then, epoxy resin 71 is cut, and then forms weld flange 62 on the upper surface of lug electrode 57.At last, by a cutting step, the silicon chip 52 in wafer state is divided into independent semiconductor chip so that obtain independent semiconductor device 51, and each structure as shown in figure 10.
In the 3rd above-mentioned embodiment, three kinds of mutual different silica dioxide granules of particle diameter are used and are used to form the diaphragm seal that is essentially four-layer structure.Replacedly, five or more kinds of particle diameter mutually different silica dioxide granules be used to be used to form and be essentially five or the diaphragm seal of more multi-layered structure.
In the second and the 3rd above-mentioned embodiment, on the lug electrode 57 of semiconductor device 51, form weld flange 62.Replacedly, can on the connection welding 32 of distribution substrate 32, form this weld flange.
And, in the above-described embodiments, form diaphragm seal 23,24,58,79 on the silicon chip 21,52 in a wafer state, then cut this silicon chip and be used to prepare independent semiconductor chip.Replacedly, can on the silicon chip in the wafer state, form diaphragm seal.In the case, expectation will be installed in by the frame spline structure that for example epoxy resin is made silicon chip in the chip status around so that prevent the upper surface of the silicon chip of encapsulant from wafer state and flow out.
For those skilled in the art, other advantage and remodeling are obvious.Therefore, the present invention is not limited to above-mentioned concrete details and representational embodiment in a broad sense.Therefore, under the prerequisite that does not break away from the spirit and scope of the present invention that define by appended claim and equivalent thereof, can make various remodeling.

Claims (20)

1, a kind of semiconductor device comprises:
The semiconductor substrate;
The a plurality of lug electrodes that on this semiconductor chip, form; And
A diaphragm seal that on the described semiconductor chip between the adjacent lug electrode, forms,
One predetermined properties of described diaphragm seal is different on its thickness direction, so that approach the characteristic of the part of this semiconductor chip more approaches this semiconductor chip than the characteristic of the part that is away from this semiconductor chip in the sealing film characteristic in the sealing film.
2, according to the semiconductor device of claim 1, wherein said predetermined properties comprises at least one in thermal coefficient of expansion and the modulus of elasticity.
3, according to the semiconductor device of claim 1, wherein:
Described diaphragm seal comprises a plurality of layers that stack;
In each layer of sealing film, comprise the particle that is used to reduce thermal coefficient of expansion at least;
These layers of sealing film are different mutually on the volume ratio of the particle that is used to reduce thermal coefficient of expansion; And
The volume ratio that approaches the particle that being used in the layer of sealing film of semiconductor chip reduce thermal coefficient of expansion is greater than the volume ratio of particle that is used to reduce thermal coefficient of expansion away from the layer of the sealing film of semiconductor chip.
4, according to the semiconductor device of claim 3, the height of the upper surface of wherein said diaphragm seal is lower than the height of the upper surface of described lug electrode.
5,, approach the characteristic of described lug electrode in described a plurality of layers of wherein said diaphragm seal apart from the characteristic of described semiconductor chip farthest side layer according to the semiconductor device of claim 3.
6, according to the semiconductor device of claim 5, the wherein said particle that is used to reduce thermal coefficient of expansion is a silica dioxide granule.
7, according to the semiconductor device of claim 1, wherein said diaphragm seal is made up of a single resin molding of particle that is used to reduce thermal coefficient of expansion that is mixed with not on the same group, and described group particle is different mutually and be distributed so that the thermal coefficient of expansion of sealing film reduces gradually from the surface lateral semiconductor chip on particle diameter.
8, according to the semiconductor device of claim 7, the wherein said particle that is used to reduce thermal coefficient of expansion is a silica dioxide granule.
9, according to the semiconductor device of claim 1, wherein said diaphragm seal is made up of a single resin molding of particle that is used to reduce thermal coefficient of expansion that is mixed with not on the same group, and described group particle is different mutually and be distributed so that being used in the sealing film reduced the volume ratio of the particle of thermal coefficient of expansion increases gradually from the surface lateral semiconductor chip on particle diameter.
10, according to the semiconductor device of claim 9, the wherein said particle that is used to reduce thermal coefficient of expansion is a silica dioxide granule.
11, a kind of method of making semiconductor device, this semiconductor device comprises that a semiconductor chip and that is formed with a plurality of lug electrodes on it comprises a plurality of layers the diaphragm seal that stacks mutually, the height of the upper surface of sealing film is lower than the height of the upper surface of this lug electrode, and this method includes step:
Stack these layers, a diaphragm and a basement membrane of sealing film;
The described film that stacks is pressurizeed under the condition of heating facing to the semiconductor chip that comprises described a plurality of lug electrodes;
Make described lug electrode outstanding, the upper surface of this lug electrode is covered by described diaphragm by the sealing film; And
Peel off described basement membrane and described diaphragm from the sealing film.
12, according to the method for the making semiconductor device of claim 11, wherein:
In each layer of sealing film, comprise the particle that is used to reduce thermal coefficient of expansion at least;
These layers of sealing film are different mutually on the volume ratio of the particle that is used to reduce thermal coefficient of expansion; And
The volume ratio that approaches the particle that being used in the layer of sealing film of semiconductor chip reduce thermal coefficient of expansion is greater than the volume ratio of particle that is used to reduce thermal coefficient of expansion away from the layer of the sealing film of semiconductor chip, and the characteristic of layer that approaches the sealing film of semiconductor chip approaches the characteristic of this semiconductor chip.
13, a kind of method of making semiconductor device, this semiconductor device comprises that one is formed with the semiconductor chip of a plurality of lug electrodes on it, and a plurality of layers the diaphragm seal that stacks mutually that comprises that on the part of this semiconductor chip between the adjacent ribs electrode, is forming, the height of the upper surface of sealing film is lower than the height of the upper surface of described lug electrode, and this method includes step:
Comprising these layers, a diaphragm and the basement membrane that stack the sealing film on this semiconductor chip of described lug electrode continuously to form the structure of a lamination, the described layer of each of sealing film, described diaphragm and described basement membrane are the forms of sheet;
The described film that stacks is pressurizeed under the condition of heating facing to the semiconductor chip that comprises described a plurality of lug electrodes;
Make described lug electrode outstanding, the upper surface of this lug electrode is covered in described diaphragm by the sealing film; And
Peel off described basement membrane and described diaphragm from the sealing film.
14, according to the method for the making semiconductor device of claim 13, wherein:
In each layer of sealing film, comprise the particle that is used to reduce thermal coefficient of expansion at least;
These layers of sealing film are different mutually on the volume ratio of the particle that is used to reduce thermal coefficient of expansion; And
The volume ratio that approaches the particle that being used in the layer of sealing film of semiconductor chip reduce thermal coefficient of expansion is greater than the volume ratio of particle that is used to reduce thermal coefficient of expansion away from the layer of the sealing film of semiconductor chip, and the characteristic of layer that approaches the sealing film of semiconductor chip approaches the characteristic of this semiconductor chip.
15, a kind of method of making semiconductor device, this semiconductor device comprises and is formed on the on-chip a plurality of lug electrodes of semiconductor, and at a plurality of layers the diaphragm seal that stacks mutually that comprises that forms on the part of this semiconductor chip between the adjacent ribs electrode, this method includes step:
Forming a bottom sealant on the part of this semiconductor chip between the adjacent ribs electrode, described lower encapsulant layer is to advance the thermal coefficient of expansion that thermal coefficient of expansion that a resin is used to make described lower encapsulant layer approaches semiconductor chip by the particulate dispersion that will be used for reducing thermal coefficient of expansion to be formed;
Shown in form an intermediate seal layer on the lower encapsulant layer, described intermediate seal layer is to advance thermal coefficient of expansion that a resin is used to make described intermediate seal layer by the particulate dispersion that will be used for reducing thermal coefficient of expansion to be formed less than the thermal coefficient of expansion of this resin and greater than the thermal coefficient of expansion of this lower encapsulant layer; And
On described intermediate seal layer, form a top seal layer of only forming by a resin.
16, according to the method for the making semiconductor device of claim 15, the wherein said particle that is used to reduce thermal coefficient of expansion is a silica dioxide granule.
17, a kind of method of making semiconductor device, this semiconductor device comprise and are formed on the on-chip a plurality of lug electrodes of semiconductor, and at a diaphragm seal that forms on the part of this semiconductor chip between the adjacent ribs electrode, this method includes step:
Forming a single resin molding on the part of this semiconductor chip between the adjacent ribs electrode, the particle that is used for reducing thermal coefficient of expansion on the same group is not dispersed in described resin molding, and described group particle is different mutually on particle diameter; And
Form described diaphragm seal by making this resin molding that is mixed with the particle that is used to reduce thermal coefficient of expansion have the thermal coefficient of expansion that reduces gradually to this semiconductor chip from this surface resin film.
18, according to the method for the making semiconductor device of claim 17, the wherein said particle that is used to reduce thermal coefficient of expansion is a silica dioxide granule.
19, a kind of method of making semiconductor device, this semiconductor device comprise and are formed on the on-chip a plurality of lug electrodes of semiconductor, and at a diaphragm seal that forms on the part of this semiconductor chip between the adjacent ribs electrode, this method includes step:
Forming a single resin molding on the part of this semiconductor chip between the adjacent ribs electrode, the particle that is used for reducing thermal coefficient of expansion on the same group is not dispersed in described resin molding, and described group particle is different mutually on particle diameter; And
Recently form described diaphragm seal by making this resin molding that is mixed with the particle that is used to reduce thermal coefficient of expansion have the volume that reduces the particle of thermal coefficient of expansion to this semiconductor chip being used to of increasing gradually from this surface resin film.
20, according to the method for the making semiconductor device of claim 19, the wherein said particle that is used to reduce thermal coefficient of expansion is a silica dioxide granule.
CNB001007556A 1999-02-03 2000-02-03 Semiconductor device and manufacture method Expired - Lifetime CN1246900C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP02593499A JP3346320B2 (en) 1999-02-03 1999-02-03 Semiconductor device and manufacturing method thereof
JP25934/1999 1999-02-03

Publications (2)

Publication Number Publication Date
CN1264173A CN1264173A (en) 2000-08-23
CN1246900C true CN1246900C (en) 2006-03-22

Family

ID=12179615

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB001007556A Expired - Lifetime CN1246900C (en) 1999-02-03 2000-02-03 Semiconductor device and manufacture method

Country Status (5)

Country Link
US (1) US6600234B2 (en)
JP (1) JP3346320B2 (en)
KR (1) KR100394965B1 (en)
CN (1) CN1246900C (en)
TW (1) TW439160B (en)

Families Citing this family (98)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6642136B1 (en) 2001-09-17 2003-11-04 Megic Corporation Method of making a low fabrication cost, high performance, high reliability chip scale package
US8021976B2 (en) * 2002-10-15 2011-09-20 Megica Corporation Method of wire bonding over active area of a semiconductor circuit
US10388626B2 (en) * 2000-03-10 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming flipchip interconnect structure
EP1278612B1 (en) 2000-03-10 2010-02-24 Chippac, Inc. Flip chip Interconnection structure and method of obtaining the same
US7247932B1 (en) * 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
US6815324B2 (en) * 2001-02-15 2004-11-09 Megic Corporation Reliable metal bumps on top of I/O pads after removal of test probe marks
TWI313507B (en) 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US8158508B2 (en) * 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
JP2002353347A (en) * 2001-05-24 2002-12-06 Oki Electric Ind Co Ltd Semiconductor device and method of manufacturing same
US7099293B2 (en) * 2002-05-01 2006-08-29 Stmicroelectronics, Inc. Buffer-less de-skewing for symbol combination in a CDMA demodulator
TWI245402B (en) 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
JP3829325B2 (en) * 2002-02-07 2006-10-04 日本電気株式会社 Semiconductor element, manufacturing method thereof, and manufacturing method of semiconductor device
DE10392377T5 (en) * 2002-03-12 2005-05-12 FAIRCHILD SEMICONDUCTOR CORP. (n.d.Ges.d. Staates Delaware) Wafer level coated pin-like bumps made of copper
JP4126389B2 (en) * 2002-09-20 2008-07-30 カシオ計算機株式会社 Manufacturing method of semiconductor package
US7285867B2 (en) * 2002-11-08 2007-10-23 Casio Computer Co., Ltd. Wiring structure on semiconductor substrate and method of fabricating the same
DE10301934A1 (en) * 2003-01-20 2004-07-29 Epcos Ag Electrical component used as a BAW or SAW arrangement comprises a substrate with component structures on which are arranged solder metallizations electrically connected to the component structures
JP3983205B2 (en) * 2003-07-08 2007-09-26 沖電気工業株式会社 Semiconductor device and manufacturing method thereof
KR100886292B1 (en) 2003-09-09 2009-03-04 산요덴키가부시키가이샤 Semiconductor module and semiconductor device including circuit components, manufacturing method and display device thereof
TWI358776B (en) * 2003-11-08 2012-02-21 Chippac Inc Flip chip interconnection pad layout
US8853001B2 (en) 2003-11-08 2014-10-07 Stats Chippac, Ltd. Semiconductor device and method of forming pad layout for flipchip semiconductor die
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US7659633B2 (en) 2004-11-10 2010-02-09 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
USRE44500E1 (en) 2003-11-10 2013-09-17 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
KR101249555B1 (en) 2003-11-10 2013-04-01 스태츠 칩팩, 엘티디. Bump-on-lead flip chip interconnection
US8216930B2 (en) * 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US20070105277A1 (en) 2004-11-10 2007-05-10 Stats Chippac Ltd. Solder joint flip chip interconnection
US8129841B2 (en) * 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
US8350384B2 (en) * 2009-11-24 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US8574959B2 (en) * 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US8076232B2 (en) * 2008-04-03 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
JP3953027B2 (en) * 2003-12-12 2007-08-01 ソニー株式会社 Semiconductor device and manufacturing method thereof
TWI245350B (en) * 2004-03-25 2005-12-11 Siliconware Precision Industries Co Ltd Wafer level semiconductor package with build-up layer
US7170188B2 (en) * 2004-06-30 2007-01-30 Intel Corporation Package stress management
CN100395886C (en) * 2004-07-16 2008-06-18 新光电气工业株式会社 Semiconductor device manufacturing method
US8067837B2 (en) * 2004-09-20 2011-11-29 Megica Corporation Metallization structure over passivation layer for IC chip
JP4016984B2 (en) 2004-12-21 2007-12-05 セイコーエプソン株式会社 Semiconductor device, semiconductor device manufacturing method, circuit board, and electronic device
US8294279B2 (en) 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
WO2006105015A2 (en) 2005-03-25 2006-10-05 Stats Chippac Ltd. Flip chip interconnection having narrow interconnection sites on the substrate
US9258904B2 (en) * 2005-05-16 2016-02-09 Stats Chippac, Ltd. Semiconductor device and method of forming narrow interconnect sites on substrate with elongated mask openings
US20060255473A1 (en) 2005-05-16 2006-11-16 Stats Chippac Ltd. Flip chip interconnect solder mask
JP4757056B2 (en) * 2006-02-21 2011-08-24 富士通株式会社 Resin layer forming method, semiconductor device and manufacturing method thereof
JP2007250952A (en) * 2006-03-17 2007-09-27 Sanken Electric Co Ltd Semiconductor device and manufacturing method therefor
US9847309B2 (en) 2006-09-22 2017-12-19 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate
US7713782B2 (en) * 2006-09-22 2010-05-11 Stats Chippac, Inc. Fusible I/O interconnection systems and methods for flip-chip packaging involving substrate-mounted stud-bumps
US20080203557A1 (en) * 2007-01-30 2008-08-28 Sanyo Electric Co., Ltd. Semiconductor module and method of manufacturing the same
US7820543B2 (en) * 2007-05-29 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Enhanced copper posts for wafer level chip scale packaging
US20090014852A1 (en) * 2007-07-11 2009-01-15 Hsin-Hui Lee Flip-Chip Packaging with Stud Bumps
KR101161061B1 (en) 2007-08-08 2012-07-02 가부시키가이샤 테라미크로스 Semiconductor device and method for manufacturing the same
JP4752825B2 (en) 2007-08-24 2011-08-17 カシオ計算機株式会社 Manufacturing method of semiconductor device
US8492263B2 (en) 2007-11-16 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Protected solder ball joints in wafer level chip-scale packaging
US8349721B2 (en) 2008-03-19 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
US7759137B2 (en) * 2008-03-25 2010-07-20 Stats Chippac, Ltd. Flip chip interconnection structure with bump on partial pad and method thereof
US9345148B2 (en) 2008-03-25 2016-05-17 Stats Chippac, Ltd. Semiconductor device and method of forming flipchip interconnection structure with bump on partial pad
JP5081037B2 (en) * 2008-03-31 2012-11-21 ラピスセミコンダクタ株式会社 Semiconductor device
US20090250814A1 (en) * 2008-04-03 2009-10-08 Stats Chippac, Ltd. Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof
US7897502B2 (en) 2008-09-10 2011-03-01 Stats Chippac, Ltd. Method of forming vertically offset bond on trace interconnects on recessed and raised bond fingers
US8198186B2 (en) 2008-12-31 2012-06-12 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material during reflow with solder mask patch
US8659172B2 (en) * 2008-12-31 2014-02-25 Stats Chippac, Ltd. Semiconductor device and method of confining conductive bump material with solder mask patch
US20100237500A1 (en) * 2009-03-20 2010-09-23 Stats Chippac, Ltd. Semiconductor Substrate and Method of Forming Conformal Solder Wet-Enhancement Layer on Bump-on-Lead Site
TWI445147B (en) * 2009-10-14 2014-07-11 Advanced Semiconductor Eng Semiconductor device
TW201113962A (en) * 2009-10-14 2011-04-16 Advanced Semiconductor Eng Chip having metal pillar structure
US8299616B2 (en) * 2010-01-29 2012-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. T-shaped post for semiconductor devices
US8318596B2 (en) 2010-02-11 2012-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8803319B2 (en) 2010-02-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar structure having a non-planar surface for semiconductor devices
US8039384B2 (en) 2010-03-09 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces
US8409978B2 (en) 2010-06-24 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset bond on trace interconnect structure on leadframe
US8241963B2 (en) 2010-07-13 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed pillar structure
US8492197B2 (en) 2010-08-17 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
US8435834B2 (en) 2010-09-13 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP
TWI478303B (en) 2010-09-27 2015-03-21 Advanced Semiconductor Eng Chip having metal pillar and package having the same
TWI451546B (en) 2010-10-29 2014-09-01 Advanced Semiconductor Eng Stacked semiconductor package, semiconductor package thereof and method for making a semiconductor package
US20120112336A1 (en) * 2010-11-05 2012-05-10 Guzek John S Encapsulated die, microelectronic package containing same, and method of manufacturing said microelectronic package
US9030019B2 (en) * 2010-12-14 2015-05-12 Infineon Technologies Ag Semiconductor device and method of manufacture thereof
US8492203B2 (en) * 2011-01-21 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers
US10204879B2 (en) 2011-01-21 2019-02-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming wafer-level interconnect structures with advanced dielectric characteristics
US8598691B2 (en) * 2011-09-09 2013-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacturing and packaging thereof
US8780576B2 (en) 2011-09-14 2014-07-15 Invensas Corporation Low CTE interposer
US9978656B2 (en) * 2011-11-22 2018-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming fine-pitch copper bump structures
WO2013095363A1 (en) * 2011-12-20 2013-06-27 Intel Corporation Microelectronic package and stacked microelectronic assembly and computing system containing same
US9230932B2 (en) 2012-02-09 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect crack arrestor structure and methods
US9515036B2 (en) 2012-04-20 2016-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for solder connections
US8884443B2 (en) 2012-07-05 2014-11-11 Advanced Semiconductor Engineering, Inc. Substrate for semiconductor package and process for manufacturing
US8823168B2 (en) * 2012-08-31 2014-09-02 Texas Instruments Incorporated Die underfill structure and method
US8686568B2 (en) 2012-09-27 2014-04-01 Advanced Semiconductor Engineering, Inc. Semiconductor package substrates having layered circuit segments, and related methods
US9293438B2 (en) 2013-07-03 2016-03-22 Harris Corporation Method for making electronic device with cover layer with openings and related devices
US8883563B1 (en) * 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
JP7095978B2 (en) * 2017-11-16 2022-07-05 日東電工株式会社 Semiconductor process sheet and semiconductor package manufacturing method
KR20210003620A (en) * 2019-07-02 2021-01-12 주성엔지니어링(주) Apparatus for processing substrate
US11417606B2 (en) * 2019-09-26 2022-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
JP2021106191A (en) * 2019-12-26 2021-07-26 株式会社ノベルクリスタルテクノロジー Semiconductor element and method of manufacturing the same, and semiconductor device and method of manufacturing the same
CN112844982A (en) * 2020-12-31 2021-05-28 格至控智能动力科技（上海）有限公司 Glue pouring method in high-airtight environment

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0793343B2 (en) 1987-12-28 1995-10-09 松下電器産業株式会社 Method for manufacturing semiconductor device
JP2830351B2 (en) 1990-04-12 1998-12-02 カシオ計算機株式会社 Semiconductor device connection method
US5641997A (en) * 1993-09-14 1997-06-24 Kabushiki Kaisha Toshiba Plastic-encapsulated semiconductor device
US5864178A (en) * 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
JP3146345B2 (en) * 1996-03-11 2001-03-12 アムコー テクノロジー コリア インコーポレーティド Bump forming method for bump chip scale semiconductor package
US5880530A (en) * 1996-03-29 1999-03-09 Intel Corporation Multiregion solder interconnection structure
JP3293740B2 (en) 1996-06-24 2002-06-17 矢崎総業株式会社 Automotive roof module
JP2848357B2 (en) * 1996-10-02 1999-01-20 日本電気株式会社 Semiconductor device mounting method and its mounting structure
US6335571B1 (en) * 1997-07-21 2002-01-01 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
DE1025587T1 (en) * 1997-07-21 2001-02-08 Aguila Technologies, Inc. SEMICONDUCTOR FLIPCHIP PACK AND PRODUCTION METHOD THEREFOR
JPH11204692A (en) * 1998-01-19 1999-07-30 Oki Electric Ind Co Ltd Semiconductor device
JP3516592B2 (en) * 1998-08-18 2004-04-05 沖電気工業株式会社 Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
CN1264173A (en) 2000-08-23
TW439160B (en) 2001-06-07
US6600234B2 (en) 2003-07-29
US20020000658A1 (en) 2002-01-03
KR100394965B1 (en) 2003-08-19
KR20000057893A (en) 2000-09-25
JP3346320B2 (en) 2002-11-18
JP2000223518A (en) 2000-08-11

Similar Documents

Publication Publication Date Title
CN1246900C (en) Semiconductor device and manufacture method
CN1038465C (en) Metal base board and elecronic equipment using the same
US20060165978A1 (en) Insulating sheet and method for producing it, and power module comprising the insulating sheet
US8580617B2 (en) Thermosetting die-bonding film
US20040213973A1 (en) Film adhesive for sealing, film laminate for sealing and sealing method
TW201001565A (en) Multifunction tape for semiconductor package and method of fabricating semiconductor device using the same
US8008124B2 (en) Adhesive film for semiconductor and semiconductor device using the adhesive film
CN1674280A (en) Stacked electronic part
CN1649119A (en) Semiconductor device
US20110049701A1 (en) Semiconductor device and method of manufacturing the same
KR102525372B1 (en) Manufacturing method of mounting structure and sheet used therein
TW201500197A (en) Thermosetting sealing resin sheet and method for producing electronic component package
US6242799B1 (en) Anisotropic stress buffer and semiconductor device using the same
CN107154423B (en) Array substrate, manufacturing method thereof and display device
JPH10289969A (en) Semiconductor device and sealing resin sheet for use therefor
CN1144284C (en) Semiconductor device and manufacture thereof
CN1317761C (en) Flip chip packaging joint structure and method for manufacturing same
JP7442763B2 (en) release film
US20060038276A1 (en) Methods and systems for attaching die in stacked-die packages
WO2022004849A1 (en) Semiconductor device and method for producing same
CN1788530A (en) Flexible circuit board, method for making the same, flexible multi-layer wiring circuit board, and method for making the same
WO2020217395A1 (en) Semiconductor device having dolmen structure and method for manufacturing same, method for manufacturing support piece, and laminate film for support piece formation
CN106912159B (en) Insulating resin sheet and the printed circuit board for using the insulating resin sheet
JP2009135506A (en) Adhesive film, use of the same, and method of manufacturing semiconductor device
KR100755127B1 (en) Film for die bonding, packaging method for semiconductor chip and semiconductor chip package using the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
REG Reference to a national code

Ref country code: HK

Ref legal event code: GR

Ref document number: 1067231

Country of ref document: HK

ASS Succession or assignment of patent right

Owner name: ZHAOZHUANGWEI CO., LTD.

Free format text: FORMER OWNER: CASIO COMPUTER CO., LTD.

Effective date: 20120316

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20120316

Address after: Tokyo, Japan

Patentee after: Zhaozhuang Micro Co.,Ltd.

Address before: Tokyo, Japan

Patentee before: CASIO COMPUTER Co.,Ltd.

TR01 Transfer of patent right

Effective date of registration: 20170406

Address after: Kagawa

Patentee after: AOI ELECTRONICS Co.,Ltd.

Address before: Kanagawa

Patentee before: Zhao Tan Jing Co.,Ltd.

Effective date of registration: 20170406

Address after: Kanagawa

Patentee after: Zhao Tan Jing Co.,Ltd.

Address before: Tokyo, Japan

Patentee before: Zhaozhuang Micro Co.,Ltd.

TR01 Transfer of patent right
CX01 Expiry of patent term

Granted publication date: 20060322

CX01 Expiry of patent term