JPH0571134B2 - - Google Patents
Info
- Publication number
- JPH0571134B2 JPH0571134B2 JP60064023A JP6402385A JPH0571134B2 JP H0571134 B2 JPH0571134 B2 JP H0571134B2 JP 60064023 A JP60064023 A JP 60064023A JP 6402385 A JP6402385 A JP 6402385A JP H0571134 B2 JPH0571134 B2 JP H0571134B2
- Authority
- JP
- Japan
- Prior art keywords
- mask
- gate
- crystal substrate
- semiconductor crystal
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
- H10D64/0133—Aspects related to lithography, isolation or planarisation of the conductor at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
- H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
- H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
- H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/082—Ion implantation FETs/COMs
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/623,810 US4532698A (en) | 1984-06-22 | 1984-06-22 | Method of making ultrashort FET using oblique angle metal deposition and ion implantation |
| US623810 | 1984-06-22 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6112077A JPS6112077A (ja) | 1986-01-20 |
| JPH0571134B2 true JPH0571134B2 (enExample) | 1993-10-06 |
Family
ID=24499485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60064023A Granted JPS6112077A (ja) | 1984-06-22 | 1985-03-29 | 半導体構造体の製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4532698A (enExample) |
| EP (1) | EP0179196B1 (enExample) |
| JP (1) | JPS6112077A (enExample) |
| DE (1) | DE3567320D1 (enExample) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2566186B1 (fr) * | 1984-06-14 | 1986-08-29 | Thomson Csf | Procede de fabrication d'au moins un transistor a effet de champ en couche mince et transistor obtenu par ce procede |
| US4649638A (en) * | 1985-04-17 | 1987-03-17 | International Business Machines Corp. | Construction of short-length electrode in semiconductor device |
| US4640003A (en) * | 1985-09-30 | 1987-02-03 | The United States Of America As Represented By The Secretary Of The Navy | Method of making planar geometry Schottky diode using oblique evaporation and normal incidence proton bombardment |
| US4839704A (en) * | 1987-09-16 | 1989-06-13 | National Semiconductor Corporation | Application of deep-junction non-self-aligned transistors for suppressing hot carriers |
| JPH022142A (ja) * | 1988-06-13 | 1990-01-08 | Mitsubishi Electric Corp | 電界効果トランジスタ及びその製造方法 |
| JPH0748503B2 (ja) * | 1988-11-29 | 1995-05-24 | 三菱電機株式会社 | 電界効果トランジスタの製造方法 |
| EP0416141A1 (de) * | 1989-09-04 | 1991-03-13 | Siemens Aktiengesellschaft | Verfahren zur Herstellung eines FET mit asymmetrisch angeordnetem Gate-Bereich |
| US5202272A (en) * | 1991-03-25 | 1993-04-13 | International Business Machines Corporation | Field effect transistor formed with deep-submicron gate |
| US5219772A (en) * | 1991-08-15 | 1993-06-15 | At&T Bell Laboratories | Method for making field effect devices with ultra-short gates |
| US5391510A (en) * | 1992-02-28 | 1995-02-21 | International Business Machines Corporation | Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps |
| FR2694449B1 (fr) * | 1992-07-09 | 1994-10-28 | France Telecom | Composant électronique multifonctions, notamment élément à résistance dynamique négative, et procédé de fabrication correspondant. |
| DE4441723A1 (de) * | 1994-11-23 | 1996-05-30 | Siemens Ag | Herstellungsverfahren für Gate-Elektroden von MOSFETs |
| US5885425A (en) * | 1995-06-06 | 1999-03-23 | International Business Machines Corporation | Method for selective material deposition on one side of raised or recessed features |
| KR100221627B1 (ko) * | 1996-07-29 | 1999-09-15 | 구본준 | 반도체장치 및 그의 제조방법 |
| US6025208A (en) * | 1997-08-27 | 2000-02-15 | The Board Of Trustees Of The Leland Stanford Junior University | Method of making electrical elements on the sidewalls of micromechanical structures |
| US20020063263A1 (en) * | 2000-11-30 | 2002-05-30 | Scott David B. | Metal oxide semiconductor transistor with self-aligned channel implant |
| TWI228297B (en) * | 2003-12-12 | 2005-02-21 | Richtek Techohnology Corp | Asymmetrical cellular metal-oxide semiconductor transistor array |
| CN101536153B (zh) * | 2006-11-06 | 2011-07-20 | Nxp股份有限公司 | 制造fet栅极的方法 |
| CN102179691A (zh) * | 2011-05-11 | 2011-09-14 | 西安飞机工业(集团)有限责任公司 | 飞机发动机安装装置及飞机发动机安装方法 |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3873371A (en) * | 1972-11-07 | 1975-03-25 | Hughes Aircraft Co | Small geometry charge coupled device and process for fabricating same |
| US3846822A (en) * | 1973-10-05 | 1974-11-05 | Bell Telephone Labor Inc | Methods for making field effect transistors |
| US4232439A (en) * | 1976-11-30 | 1980-11-11 | Vlsi Technology Research Association | Masking technique usable in manufacturing semiconductor devices |
| US4093503A (en) * | 1977-03-07 | 1978-06-06 | International Business Machines Corporation | Method for fabricating ultra-narrow metallic lines |
| US4135289A (en) * | 1977-08-23 | 1979-01-23 | Bell Telephone Laboratories, Incorporated | Method for producing a buried junction memory device |
| JPS5939906B2 (ja) * | 1978-05-04 | 1984-09-27 | 超エル・エス・アイ技術研究組合 | 半導体装置の製造方法 |
| DE2821975C2 (de) * | 1978-05-19 | 1983-01-27 | Siemens AG, 1000 Berlin und 8000 München | Metall-Halbleiter-Feldeffekttransistor (MESFET) und Verfahren zu dessen Herstellung |
| US4313782A (en) * | 1979-11-14 | 1982-02-02 | Rca Corporation | Method of manufacturing submicron channel transistors |
| US4377899A (en) * | 1979-11-19 | 1983-03-29 | Sumitomo Electric Industries, Ltd. | Method of manufacturing Schottky field-effect transistors utilizing shadow masking |
| US4358340A (en) * | 1980-07-14 | 1982-11-09 | Texas Instruments Incorporated | Submicron patterning without using submicron lithographic technique |
| JPS57204172A (en) * | 1981-06-08 | 1982-12-14 | Ibm | Field effect transistor |
| US4430791A (en) * | 1981-12-30 | 1984-02-14 | International Business Machines Corporation | Sub-micrometer channel length field effect transistor process |
| US4417385A (en) * | 1982-08-09 | 1983-11-29 | General Electric Company | Processes for manufacturing insulated-gate semiconductor devices with integral shorts |
| JPS59124172A (ja) * | 1982-12-30 | 1984-07-18 | インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン | Fet製造方法 |
-
1984
- 1984-06-22 US US06/623,810 patent/US4532698A/en not_active Expired - Lifetime
-
1985
- 1985-03-29 JP JP60064023A patent/JPS6112077A/ja active Granted
- 1985-06-13 EP EP85107231A patent/EP0179196B1/en not_active Expired
- 1985-06-13 DE DE8585107231T patent/DE3567320D1/de not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| US4532698A (en) | 1985-08-06 |
| EP0179196A3 (en) | 1987-07-22 |
| DE3567320D1 (en) | 1989-02-09 |
| EP0179196A2 (en) | 1986-04-30 |
| JPS6112077A (ja) | 1986-01-20 |
| EP0179196B1 (en) | 1989-01-04 |
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