JPH0530064B2 - - Google Patents

Info

Publication number
JPH0530064B2
JPH0530064B2 JP59167245A JP16724584A JPH0530064B2 JP H0530064 B2 JPH0530064 B2 JP H0530064B2 JP 59167245 A JP59167245 A JP 59167245A JP 16724584 A JP16724584 A JP 16724584A JP H0530064 B2 JPH0530064 B2 JP H0530064B2
Authority
JP
Japan
Prior art keywords
forming
insulating
layer
epitaxial layer
insulating region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59167245A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6052037A (ja
Inventor
Ai Kaminzu Seodooru
Aaru Buratsudobarii Donarudo
Ai Doroorei Kurifuoodo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JPS6052037A publication Critical patent/JPS6052037A/ja
Publication of JPH0530064B2 publication Critical patent/JPH0530064B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1912—Preparing SOI wafers using selective deposition, e.g. epitaxial lateral overgrowth [ELO] or selective deposition of single crystal silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated

Landscapes

  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
JP59167245A 1983-08-12 1984-08-09 半導体装置の製法 Granted JPS6052037A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/522,767 US4507158A (en) 1983-08-12 1983-08-12 Trench isolated transistors in semiconductor films
US522767 1990-05-14

Publications (2)

Publication Number Publication Date
JPS6052037A JPS6052037A (ja) 1985-03-23
JPH0530064B2 true JPH0530064B2 (https=) 1993-05-07

Family

ID=24082260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59167245A Granted JPS6052037A (ja) 1983-08-12 1984-08-09 半導体装置の製法

Country Status (2)

Country Link
US (1) US4507158A (https=)
JP (1) JPS6052037A (https=)

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6072243A (ja) * 1983-09-28 1985-04-24 Matsushita Electric Ind Co Ltd 半導体集積回路装置
KR900001267B1 (ko) * 1983-11-30 1990-03-05 후지쓰 가부시끼가이샤 Soi형 반도체 장치의 제조방법
US4570330A (en) * 1984-06-28 1986-02-18 Gte Laboratories Incorporated Method of producing isolated regions for an integrated circuit substrate
US4860081A (en) * 1984-06-28 1989-08-22 Gte Laboratories Incorporated Semiconductor integrated circuit structure with insulative partitions
US4631570A (en) * 1984-07-03 1986-12-23 Motorola, Inc. Integrated circuit having buried oxide isolation and low resistivity substrate for power supply interconnection
FR2571544B1 (fr) * 1984-10-05 1987-07-31 Haond Michel Procede de fabrication d'ilots de silicium monocristallin isoles electriquement les uns des autres
US4593458A (en) * 1984-11-02 1986-06-10 General Electric Company Fabrication of integrated circuit with complementary, dielectrically-isolated, high voltage semiconductor devices
US4551394A (en) * 1984-11-26 1985-11-05 Honeywell Inc. Integrated three-dimensional localized epitaxial growth of Si with localized overgrowth of GaAs
US4619033A (en) * 1985-05-10 1986-10-28 Rca Corporation Fabricating of a CMOS FET with reduced latchup susceptibility
US4717677A (en) * 1985-08-19 1988-01-05 Motorola Inc. Fabricating a semiconductor device with buried oxide
US4947227A (en) * 1985-09-16 1990-08-07 Texas Instruments, Incorporated Latch-up resistant CMOS structure
US5049519A (en) * 1985-09-16 1991-09-17 Texas Instruments Incorporated Latch-up resistant CMOS process
JPS6276645A (ja) * 1985-09-30 1987-04-08 Toshiba Corp 複合半導体結晶体構造
US4824795A (en) * 1985-12-19 1989-04-25 Siliconix Incorporated Method for obtaining regions of dielectrically isolated single crystal silicon
EP0227523A3 (en) * 1985-12-19 1989-05-31 SILICONIX Incorporated Method for obtaining regions of dielectrically isolated single crystal silicon
US4818337A (en) * 1986-04-11 1989-04-04 University Of Delaware Thin active-layer solar cell with multiple internal reflections
AU588700B2 (en) * 1986-06-30 1989-09-21 Canon Kabushiki Kaisha Semiconductor device and method for producing the same
US4749441A (en) * 1986-12-11 1988-06-07 General Motors Corporation Semiconductor mushroom structure fabrication
US5059547A (en) * 1986-12-20 1991-10-22 Kabushiki Kaisha Toshiba Method of manufacturing double diffused mosfet with potential biases
US4760036A (en) * 1987-06-15 1988-07-26 Delco Electronics Corporation Process for growing silicon-on-insulator wafers using lateral epitaxial growth with seed window oxidation
US5059544A (en) * 1988-07-14 1991-10-22 International Business Machines Corp. Method of forming bipolar transistor having self-aligned emitter-base using selective and non-selective epitaxy
US5061644A (en) * 1988-12-22 1991-10-29 Honeywell Inc. Method for fabricating self-aligned semiconductor devices
US5146304A (en) * 1988-12-22 1992-09-08 Honeywell Inc. Self-aligned semiconductor device
JPH0822591B2 (ja) * 1989-02-10 1996-03-06 株式会社東京機械製作所 印刷機におけるインキ供給装置
US5234861A (en) * 1989-06-30 1993-08-10 Honeywell Inc. Method for forming variable width isolation structures
US5017999A (en) * 1989-06-30 1991-05-21 Honeywell Inc. Method for forming variable width isolation structures
US5049521A (en) * 1989-11-30 1991-09-17 Silicon General, Inc. Method for forming dielectrically isolated semiconductor devices with contact to the wafer substrate
US5296392A (en) * 1990-03-06 1994-03-22 Digital Equipment Corporation Method of forming trench isolated regions with sidewall doping
US5065217A (en) * 1990-06-27 1991-11-12 Texas Instruments Incorporated Process for simultaneously fabricating isolation structures for bipolar and CMOS circuits
US5137837A (en) * 1990-08-20 1992-08-11 Hughes Aircraft Company Radiation-hard, high-voltage semiconductive device structure fabricated on SOI substrate
US5143862A (en) * 1990-11-29 1992-09-01 Texas Instruments Incorporated SOI wafer fabrication by selective epitaxial growth
JPH0697400A (ja) * 1990-11-29 1994-04-08 Texas Instr Inc <Ti> Ｓｏｉウェーハ及びその製造方法
FR2682128B1 (fr) * 1991-10-08 1993-12-03 Thomson Csf Procede de croissance de couches heteroepitaxiales.
JPH05121317A (ja) * 1991-10-24 1993-05-18 Rohm Co Ltd Ｓｏｉ構造形成方法
US5258318A (en) * 1992-05-15 1993-11-02 International Business Machines Corporation Method of forming a BiCMOS SOI wafer having thin and thick SOI regions of silicon
FR2785087B1 (fr) * 1998-10-23 2003-01-03 St Microelectronics Sa Procede de formation dans une plaquette de silicium d'un caisson isole
US6084271A (en) 1998-11-06 2000-07-04 Advanced Micro Devices, Inc. Transistor with local insulator structure
US6380019B1 (en) 1998-11-06 2002-04-30 Advanced Micro Devices, Inc. Method of manufacturing a transistor with local insulator structure
US6452233B1 (en) * 1999-03-23 2002-09-17 Citizen Watch Co., Ltd. SOI device having a leakage stopping layer
US6214653B1 (en) * 1999-06-04 2001-04-10 International Business Machines Corporation Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate
US6455903B1 (en) 2000-01-26 2002-09-24 Advanced Micro Devices, Inc. Dual threshold voltage MOSFET by local confinement of channel depletion layer using inert ion implantation
FR2819630B1 (fr) * 2001-01-12 2003-08-15 St Microelectronics Sa Dispositif semi-conducteur a zone isolee et procede de fabrication correspondant
JP2003203967A (ja) * 2001-12-28 2003-07-18 Toshiba Corp 部分ｓｏｉウェーハの製造方法、半導体装置及びその製造方法
US7329923B2 (en) * 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
DE10343132B4 (de) * 2003-09-18 2009-07-09 X-Fab Semiconductor Foundries Ag Isolierte MOS-Transistoren mit ausgedehntem Drain-Gebiet für erhöhte Spannungen
US7081397B2 (en) * 2004-08-30 2006-07-25 International Business Machines Corporation Trench sidewall passivation for lateral RIE in a selective silicon-on-insulator process flow
EP1630863B1 (en) * 2004-08-31 2014-05-14 Infineon Technologies AG Method of fabricating a monolithically integrated vertical semiconducting device in an soi substrate
US7323752B2 (en) * 2004-09-30 2008-01-29 Taiwan Semiconductor Manufacturing Co., Ltd. ESD protection circuit with floating diffusion regions
KR100566675B1 (ko) * 2004-12-14 2006-03-31 삼성전자주식회사 반도체 장치와 그 제조 방법
US8530355B2 (en) * 2005-12-23 2013-09-10 Infineon Technologies Ag Mixed orientation semiconductor device and method
DE102006024495A1 (de) * 2006-05-26 2007-11-29 Atmel Germany Gmbh Verfahren zur Herstellung einer Halbleiteranordnung, Halbleiteranordnung und deren Verwendung
CN100539024C (zh) * 2006-06-23 2009-09-09 台湾积体电路制造股份有限公司 半导体装置的形成方法
US7803690B2 (en) * 2006-06-23 2010-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxy silicon on insulator (ESOI)
US20090072355A1 (en) * 2007-09-17 2009-03-19 International Business Machines Corporation Dual shallow trench isolation structure
US7696573B2 (en) * 2007-10-31 2010-04-13 International Business Machines Corporation Multiple crystallographic orientation semiconductor structures
JP5946771B2 (ja) * 2009-12-16 2016-07-06 ナショナル セミコンダクター コーポレーションＮａｔｉｏｎａｌ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｃｏｒｐｏｒａｔｉｏｎ 半導体基板上のラージエリアガリウム窒化物又は他の窒化物ベース構造のための応力補償
US10062693B2 (en) * 2016-02-24 2018-08-28 International Business Machines Corporation Patterned gate dielectrics for III-V-based CMOS circuits
US10593600B2 (en) 2016-02-24 2020-03-17 International Business Machines Corporation Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3425879A (en) * 1965-10-24 1969-02-04 Texas Instruments Inc Method of making shaped epitaxial deposits
US3574008A (en) * 1968-08-19 1971-04-06 Trw Semiconductors Inc Mushroom epitaxial growth in tier-type shaped holes
US3634150A (en) * 1969-06-25 1972-01-11 Gen Electric Method for forming epitaxial crystals or wafers in selected regions of substrates
US4378629A (en) * 1979-08-10 1983-04-05 Massachusetts Institute Of Technology Semiconductor embedded layer technology including permeable base transistor, fabrication method
JPS5636143A (en) * 1979-08-31 1981-04-09 Hitachi Ltd Manufacture of semiconductor device
EP0191503A3 (en) * 1980-04-10 1986-09-10 Massachusetts Institute Of Technology Method of producing sheets of crystalline material
JPS56155547A (en) * 1980-05-06 1981-12-01 Nec Corp Semiconductor device
US4371421A (en) * 1981-04-16 1983-02-01 Massachusetts Institute Of Technology Lateral epitaxial growth by seeded solidification

Also Published As

Publication number Publication date
US4507158A (en) 1985-03-26
JPS6052037A (ja) 1985-03-23

Similar Documents

Publication Publication Date Title
JPH0530064B2 (https=)
US6900094B2 (en) Method of selective removal of SiGe alloys
US8097516B2 (en) Dual trench isolation for CMOS with hybrid orientations
US7023057B2 (en) CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding
US7393730B2 (en) Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same
US6855969B2 (en) Semiconductor device having a plurality of gate electrodes and manufacturing method thereof
JP2005311367A (ja) ハイブリッド結晶方位上の歪みシリコンｃｍｏｓ
US20040180478A1 (en) Silicon-on-insulator ulsi devices with multiple silicon film thicknesses
US6879000B2 (en) Isolation for SOI chip with multiple silicon film thicknesses
US4923826A (en) Method for forming dielectrically isolated transistor
US5185286A (en) Process for producing laminated semiconductor substrate
KR100296130B1 (ko) 이중막 실리콘웨이퍼를 이용한 금속-산화막-반도체 전계효과트랜지스터 제조방법
CN100361302C (zh) 混合衬底、集成半导体结构以及它们的制备方法
CN100539024C (zh) 半导体装置的形成方法
JPH06291265A (ja) 半導体装置とその製造方法
CN101262008A (zh) 半导体器件和同一芯片上集成角形器件与平面器件的方法
JPH0548108A (ja) 半導体装置およびその製造方法
JPS60105247A (ja) 半導体装置の製造方法
CN121620180A (zh) 半导体结构及其制造方法
JP2002118263A (ja) 半導体装置の製造方法
CN114038790A (zh) 保护半导体器件沟道的器件制作方法
JP2004296744A (ja) 半導体装置の製造方法
TW202531503A (zh) 複合半導體基板
KR20070090089A (ko) 반도체 장치 및 그 제조 방법
JPS63228668A (ja) 半導体装置の製造方法