JPS6052037A - 半導体装置の製法 - Google Patents

半導体装置の製法

Info

Publication number
JPS6052037A
JPS6052037A JP59167245A JP16724584A JPS6052037A JP S6052037 A JPS6052037 A JP S6052037A JP 59167245 A JP59167245 A JP 59167245A JP 16724584 A JP16724584 A JP 16724584A JP S6052037 A JPS6052037 A JP S6052037A
Authority
JP
Japan
Prior art keywords
layer
insulating
insulating layer
semiconductor
order
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59167245A
Other languages
English (en)
Other versions
JPH0530064B2 (ja
Inventor
Ai Kaminzu Seodooru
セオドール　アイ・カミンズ
Aaru Buratsudobarii Donarudo
ドナルド　アール・ブラツドバリイ
Ai Doroorei Kurifuoodo
クリフオード　アイ・ドローレイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Japan Inc
Original Assignee
Yokogawa Hewlett Packard Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hewlett Packard Ltd filed Critical Yokogawa Hewlett Packard Ltd
Publication of JPS6052037A publication Critical patent/JPS6052037A/ja
Publication of JPH0530064B2 publication Critical patent/JPH0530064B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76278—Vertical isolation by selective deposition of single crystal silicon, i.e. SEG techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、′１（導体フィルム上に溝を設けることによ
り互いに分離されたトランジスタを得る半導体装置の！
ｌｌｌｌ法に関する。
〔従来技術及びその問題点〕
集積回路を設」１する際には、互いに隣接した回路素子
間の分離を考慮に入れなければならない。
先ず、隣接した素子を分！！１１するためにｐ−ｎ接合
形が用いられた。そして、最近は局所醸化の技術により
隣接した回路素子間の横方向分離を達成していた。これ
らの技術が実用される間、回路素子を二酸化シリコンを
絶縁層で完全に包囲するための具体的な手段が摸索され
ていた。
次に、臨界的な機械研磨に慣例の誘電体分離技術を採用
すると、回路素子の集積度が低く、■、つそのコストも
高い。しかも、この技術は、集ｉｎ回路の放熱を強くす
るような特定の応用分野にのみ限定されていた。又、サ
ファイア上のシリコン（ＳＯ３）素子は広範囲に開発さ
れているが、基板のコストが高く、その的質も限定され
てｂ）るの、５利用分野が制限されている。更に、絶縁
層」二に沈積されたシリコン・フィルムの溶解及び再結
晶性については種々検討がなされたけれども、再結晶期
間における厳密な温度傾斜の実験が制限されていた。ま
た、絶縁層上のシリコン（（Ｓｏｌ）技術は、１９８０
年秋の電気化学協会の会議で、デー・デー・ラスマンが
ｒｃＶＤにおけるシリコン・ウエハア」二の酸化ストリ
ップの横方向はびこり」について討論した。
〔発明の目的〕
したがって、本発明は横方向の溝部分離を採用し、そし
て絶縁層におけるエピタキシャル・フィルムのＣＶＤに
より、隣接素子の全体の誘電体分離を形成する新規な分
ｍ＋技術を提供するものである。そのプロセスは標準の
ＶＬＳＩについて、平坦な表面をもつ最終的な構造をも
って製造するプロセスに適合している。
〔発明の４１１要〕 本発明の一実施例によれば、約０．５〜１．０マイクロ
メータの厚さで、エピタキシャルに沈積されたフィルム
は、局所酸化（Ｌ　ＯＧ　ＯＳ　）又は側壁マスク化さ
れた分ｍｆ　（Ｓ　Ｗ　Ａ　Ｍ　Ｉ　）のような従来の
横方向分離技術で分けられているが、ごく薄いフィルム
に対しては他の技術が要求されていた。
溝の分離はこれ１″）巧いフィルムに対しては適合して
おり、そして７１η部は酸化層を数マイクロメータ程度
エツチングすることで形成される。
〔発明の実施例〕
以下、図面を用いて本発明を詳述する。第１Ａ〜ＩＥ図
は本発明の一実施例による一連の１：程を示す側断面図
である。先ず、第１Ａ図において、シリコン基板１００
　、、Ｉ：に例えば二酸化シリコンから成る絶縁層１３
０が形成される。図示されていないが、ホトレジストを
含むマスク層が１ｒＩ記絶縁層１３０のある特定の領域
にわたり被覆される。次に、絶縁Ｍ１３０はノ、（板１
００の領域１３１の部分が例えばフッ止水′ＩＡ醋水溶
１ルで除去される。又、ホトレジスト・マスク（図示せ
ず）は能のプロセスのために除去するや価がなされる。
ｍ　Ｉ　８図において、第１エピタキシャル層１４３− 〇は基板１００の領域１３１にわたり形成され、そして
絶縁層１３０の」二面１４２の部分に延びる。
例えばエピタキシャル層１４０はＣＶＤ法をわずかに変
形したエピタキシャル成長法で形成される。
この変形は本出願人が同日に特許出願した明細書中にも
紹介されているが、これは二酸化シリコン絶縁層１３０
」：における多結晶シリコン核を抑圧するために、塩素
ガス（ＨＣＬ）の追加でシランを熱分解するために使用
される。
第１Ｃ図において、第２エピタキシャル層１５０が、絶
縁層１３０の露出された表面部分の残りの部分にわたり
形成される。そして、それは前記第１エピタキシャル層
１４０と本質的に平坦な表面を形成して絶縁層１３０の
部分を埋める。又、分離の状態を明確にするために、第
２エピタキシャル層１５０は単一層１５５を形成するた
めに第１エピタキシャル層１４０を延長する。
第１Ｄ図において、ホトレジストを含むマスク層（図示
せず）は、前記エピタキシャルの単一層１５５のある選
択された領域上に被覆される。溝　４− １５１．１５２は例えば反応性イオン・エツチングによ
り１ＴｉＩ記エピタキシヤルの単一層１５５の部分に形
成される。又、７＋Ｗｌ　５１．１５２はエピタキシャ
ルのｊｊｌ一層１５５の全厚さだけ絶縁層１３０に向っ
てエツチングされる。ホトレジストのマスク層（図示せ
ず）は、次に引き続き除去される。
第１Ｅ図ニオイテ、ｉＭ　１５１．１５２（７）（ｌｌ
ｌｕｔｍは、絶縁用の酸化層１６０が成長される。次に
、溝１５１．１５２の残りの部分はＣＶＤ法により多結
晶シリコン１７０で埋められる。
第２図は本発明の他の実施例によるＣ−ＭＯ５！Ｉ造を
示す側断面図である。図において、半結晶シリコン・フ
ィルム１２０は絶縁層１２５（Ｓｏｌ５の土に成長され
、そして高電圧スイッチング素子又はｐチャネルトラン
ジスタ１１０を構成してＣＭＯ５装置をシリコン・フィ
ルム１２０」−に載青し、モして１チヤネルトランジス
タ１１５から酸化層１４０及び１２５で完全に分離し、
もって画素子間の゛ラッチアップ′°を除去する。
【図面の簡単な説明】
第１Ａ図〜第１Ｅ図は本発明の一実施例による各工程を
示す半導体装置の側断面図、第２図は他の実施例による
０ＭＯ５の（支）断面図である。 １００：シリコン基板、１１０：ｐチャネル、１１５：
ｎチャネル、１２０．シリコン・フィルム、１３０：絶
縁層、１４０：第１エピタキシャル層、１５０：第２エ
ピタキシャル層、１５５：中一層、１５１．１５２＝１
＋竹、１６０：絶縁性酸化層、１７０：多結晶シリコン
。 出順人 横河・ヒユーレット・パッカード株式会社代理人　弁理
士　長　谷　川　次　男 ７− ８ｉ、ｉｏ。 コゴー１Ｃ

Claims (1)

  1. 【特許請求の範囲】 次の工程より成る半導体装置の製法。 （イ）　半導体基板−にに第１絶縁層を形成すること、 （ロ）　ある絶縁領域を形成するために前記第１絶縁層
    の一部を剥離すること、 （ハ）ｍＩ記半導体基板の表面にほぼ平行で本質的に平
    坦な表面を形成するために前記絶縁領域に半導体層を形
    成すること、 （ニ）　ｆｆ１ｌ記第１記録１絶縁面のある部分を露出
    して前記半導体層に溝部を形成するために、前記絶縁領
    域における前記半導体層の一部を剥離すること、 （ホ）　前記溝部の壁面に第２絶縁層を形成すること、 （へ）ｍＩ記１．ｖｊ部の残りの部分に固体材料を埋め
    ること。
JP59167245A 1983-08-12 1984-08-09 半導体装置の製法 Granted JPS6052037A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/522,767 US4507158A (en) 1983-08-12 1983-08-12 Trench isolated transistors in semiconductor films
US522767 1990-05-14

Publications (2)

Publication Number Publication Date
JPS6052037A true JPS6052037A (ja) 1985-03-23
JPH0530064B2 JPH0530064B2 (ja) 1993-05-07

Family

ID=24082260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59167245A Granted JPS6052037A (ja) 1983-08-12 1984-08-09 半導体装置の製法

Country Status (2)

Country Link
US (1) US4507158A (ja)
JP (1) JPS6052037A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02209243A (ja) * 1989-02-10 1990-08-20 Tokyo Kikai Seisakusho Ltd 印刷機におけるインキ供給装置

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