JPH02187054A - 混成集積回路部品の構造 - Google Patents

混成集積回路部品の構造

Info

Publication number
JPH02187054A
JPH02187054A JP1007378A JP737889A JPH02187054A JP H02187054 A JPH02187054 A JP H02187054A JP 1007378 A JP1007378 A JP 1007378A JP 737889 A JP737889 A JP 737889A JP H02187054 A JPH02187054 A JP H02187054A
Authority
JP
Japan
Prior art keywords
chip
laminate
bare chip
semiconductor chip
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1007378A
Other languages
English (en)
Other versions
JP2790640B2 (ja
Inventor
Minoru Takatani
稔 高谷
Nobunori Mochizuki
望月　宣典
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP1007378A priority Critical patent/JP2790640B2/ja
Priority to EP97200966A priority patent/EP0789390B1/en
Priority to EP19900400092 priority patent/EP0379404A3/en
Priority to DE69034095T priority patent/DE69034095T2/de
Publication of JPH02187054A publication Critical patent/JPH02187054A/ja
Application granted granted Critical
Publication of JP2790640B2 publication Critical patent/JP2790640B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
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    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、積層構造によりコンデンサ、インダクタまた
は抵抗の少なくともいずれかを内部に構成した積層体を
有する樹脂モールド型混成集積回路部品の構造に関する
。
（従来の技術） 第６図は従来の樹脂モールド型半導体チップの構造を示
す内部透視斜視図であり、トランジスタあるいはＩＣを
含む能動素子である半導体ベアチップｌは、金線等の金
属線２によってリード端子３にボンディングされ、樹脂
４内にベアチップ１、金属線２の全体およびリード端子
３の一部を内蔵するようにモールドされる。このような
モールド部品中のベアチップｌは、基板（図示せず）に
搭載され、基板上に搭載されたコンデンサ、インダクタ
、抵抗あるいはトランス等の受動素子（いずれも図示せ
ず）に基板上の導体パターンを介して接続されて例えば
発振、増幅その他の所定機能を発揮するように構成され
る。
（発明が解決しようとする課題） このような従来構造によれば、半導体チップに接続され
る受動素子を基板上に配設する必要があるため、部品点
数の低減および小型軽量化の要望に応じることが困難で
あるという問題点があった。また、基板上に半導体素子
と受動素子とを接続するための導体パターンを形成しな
ければならないため、導体パターンが複雑化すると共に
、他の導体パターンとの重なりを防止するためのパター
ン設計が困難になるという問題点があった。
本発明は、上記従来技術の問題点に鑑み１部品点数の低
減および小型軽量化の要望に応じることができ、かつ構
成が簡略化される混成集積回路の構造を提供することを
目的とする。
（課題を解決するための手段） 本発明は、上記の目的を達成するため、複合コンデンサ
、複合インダクタまたは複合抵抗の少なくともいずれか
を内蔵し、かつ側面に端子を形成した積層体を備え、該
積層体の表裏面の少なくともいずれかに、該積層体内に
形成された回路に接続されて能動素子として作用するベ
アチップからなる半導体チップを搭載し、該半導体チッ
プとそのボンディング部および前記積層体を、前記端子
に接続された外部接続用リード端子と共にモールドする
ことにより、前記積層体からなる受動素子と、前記半導
体チップからなる能動素子とをまとめて１つのチップと
して構成したことを特徴とする。
本発明において、前記基板上にベアチップとしての半導
体チップを搭載する場合、基板上に形成した金属膜上に
半導体チップを固着して搭載することが好ましい。
（作用） 本発明は、上記の構造であるから、能動素子である半導
体ベアチップと、受動素子である積層体とが所定の機能
を発揮する１つのチップとして作用する。
また、積層体上に金属膜を介して半導体チップを固着す
れば、半導体チップにおいて発生した熱は金属膜を通し
て積層体に良好に伝導され、拡散する。
（実施例） 第１図は本発明による混成集積回路部品の構造の一実施
例を示す内部透視斜視図、第２図はその断面図、第３図
および第４図はそれぞれ本発明の構造により実現される
回路例を示す図である。
第１図および第２図において、第６図と同じ符合は同じ
機能を有する部品である。６は積層体であり、内部に複
合コンデサ８と複合インダクタ９とを重ねて一体に形成
したちのである。複合コンデンサ８は、第２図に示すよ
うに、印刷法等により誘電体１０と金属膜でなる電極１
１とを交互に積層することにより、複数個のコンデンサ
を内部に形成したもので、各コンデンサの電極は、積層
体６の側面に形成された複数個の端子７のうちの所定の
ものに接続される。複合インダクタ９も。
フェライト１２と導体膜１３とを、印刷法等により積層
し、導体ｆｉ１３がコイル状または渦巻状をなすように
形成したものである。複合インダクタ９を構成する複数
のインダクタ要素の組合わせによりてトランス等を構成
する場合もある。
該積層体６の片面には、複合抵抗を有する抵抗回路１４
が形成される。該抵抗回路１４は、複合インダクタ９の
片面に形成されたガラス層１５と、その上に形成された
導体層１６および複数の抵抗層１７と、これらの表面を
覆うガラス層１８とからなる。このような抵抗回路１４
は積層体６の両面に形成される場合もある。２０は積層
体６の表面に形成されたバッドである。
前記積層体６、抵抗回路１４、バット２０、端子７は、
例えば８００℃前後で一体に焼結される。
２１は焼結された積層体６の表面に形成された金属膜、
ｌはその上に固着されたベアチップであり、金属［２１
は、金属（銀、銅、アルミニウム、モリブデン、金ある
いはパラジウム等）の厚膜印刷、蒸着、スパッタリング
等によって形成される。ベアチップｌを金属膜２１上に
固着する方法の一例として、導電ペーストを厚膜印刷に
より積層体６上に塗布し、その上にベアチップ１を載置
し、百数十度程度で加熱することにより、金属ｇｚｉを
その上にベアチップｌを固着した状態で形成する。２は
ベアチップｌとバッド２０とをボンディングする金線等
よりなる金属線である０本実施例においては、ベアチッ
プｌをａ導体６の片面に形成しているが１両面に形成す
る場合もある。
このようにベアチップｌを積層体６上に一体に搭載し、
第２図に示すように、積層体６の端子７をリード端子３
の対応するものの上に載置し、導電ペーストあるいは半
田２３等により接続し、その後、樹脂４により、積層体
６、ベアチップｌおよび金属＆！２と、リード端子３の
一部を覆うようにモールドする。なお、リード端子３は
、リード端子３となる部分を放射状に形成し、これらの
外周部を一体化した形状のリードフレームと称される打
抜き材の周辺部を、モールド後に切断し折り曲げること
によって形成される０本実施例にＳいては、リード端子
３が基板（図示せず）に設けた穴に挿入される垂直脚を
有する形状としているが、水平脚を有する表面実装型に
も形成できる。
前記ベアチップ１、複合コンデンサ８、複合インダクタ
９あるいは抵抗回路１４内のコンデンサ、インダクタあ
るいは抵抗は、積層体６の端子７等を介して相互に接続
され、第３図および第４図に例示するように、能動素子
としてのベアチップ１以外に、２点鎖＆！ａ２４に囲ま
れた部分、すなわち、複合；ンデンサ８、複合インダク
タ９および抵抗回路１４内に含まれるコンデンサ２５、
インダクタ２６および抵抗２７も１つのチップ内に含ま
せることが可能となる。なお、第３図および第４図にお
いては、上記実施例の場合よりリード端子３の数の多い
ものについて示している。
本発明において、ベアチップ１を積層体６上に固定する
手段として、接着剤を用いても良いが、上記実施例にお
いては、積層体６上に金属膜２１を介してベアチップｌ
を固着しているので、この金属膜２１がヒートシンクと
称される熱だめの役割を果たす。複合コンデンサ８を構
成する誘電体の一例である酸化チタンは、熱伝導率が０
．００６７ｗ／Ｃ１１・℃、チタン酸バリウムは０．０
０２８ｗ／ｃｍ・℃であるが、金属＄２１として銀を用
いた場合は４．１０ｗ／Ｃａｌ・℃、銅は３．８０ｗ／
ｃ識・℃と高い値であり、ベアチップｌに発生した熱は
一時金属膜２１に伝導され、その後８Ｎ層体６に拡散し
、これによりベアチップｌの熱暴走を防止することがで
きる。
なお、本発明者等は、第５図に示す混成集積回路部品を
開発している。第５図のものは、ベアチップｌを樹脂４
によりモールドして半導体チップ３０を構成し、そのリ
ード端子３１を、積層体６Ａ上に形成したバット３２に
半田３３により機械的に固定すると共に電気的に接続し
たものであり、この場合、半導体チップ３０がベアチッ
プｌより大型（Ｗｌが大）になるため、積層体６Ａもリ
ード端子３１を接続するために面積も大（ｗ２が大）と
なる、一方、本発明によれば、搭載する半導体チップｌ
がベアチップであり、かつリード端子３１を有しないの
で、積層体６を不必要に広い面積とする必要がない。
上記実施例においては、複合コンデンサ８と複合インダ
クタ９と複合抵抗を含むものについて説明したが、これ
らのいずれかのみまたはこれらのうちの２つを組合わせ
たものを積層体６が含む場合にも本発明を適用しうる。
（発明の効果） 請求項１によれば、能動素子である半導体ベアチップと
、受動素子である積層体とか所定の機ス戯を発揮する１
つのチップとしてまとめられ、樹脂によりモールドされ
ているので、半導体チップに接続される受動素子を半導
体チップ搭載基板上に配設する必要がなくなり、混成集
積回路の大幅な部品点数が低減と小型軽量化が達成され
る。
また、半導体チップ搭載基板上に半導体素子と受動素子
とを接続するための導体パターンを形成する必要がなく
なり、基板上の導体パターンが簡略化されると共に、導
体パターンの設計が容易となる。
請求項２によれば、積層体上にヒートシンクとして作用
する金属膜を介してベアチップを固着したので、ベアチ
ップにおいて生じる熱の放散が良好となり、熱暴走を防
止することができる。
【図面の簡単な説明】
第１図は本発明による混成集積回路部品の構造の一実施
例を示す内部透視斜視図、第２図はその断面図、第３図
および第４図はそれぞれ本発明により実現される回路の
例を示す回路図、第５図は本発明者等が既に開発してい
る混成集積回路部品を示す断面図、第６図は従来の樹脂
モールド型半導体チップを示す内部透視斜視図である。

Claims (2)

    【特許請求の範囲】
  1. １．　複合コンデンサ、複合インダクタまたは複合抵抗
    の少なくともいずれかを内蔵し、かつ側面に端子を形成
    した積層体を備え、該積層体の表裏面の少なくともいず
    れかに、該積層体内に形成された回路に接続されて能動
    素子として作用するベアチップからなる半導体チップを
    搭載し、該半導体チップとそのボンディング部および前
    記積層体を、前記端子に接続された外部接続用リード端
    子と共にモールドすることにより、前記積層体からなる
    受動素子と、前記半導体チップからなる能動素子とをま
    とめて１つの回路機能チップとして構成したことを特徴
    とする混成集積回路部品の構造。
  2. ２．　請求項１において、前記基板上に金属膜を形成し
    、該金属膜上に前記ベアチップでなる半導体チップを固
    着して搭載したことを特徴とする混成集積回路部品の構
    造。
JP1007378A 1989-01-14 1989-01-14 混成集積回路部品の構造 Expired - Fee Related JP2790640B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP1007378A JP2790640B2 (ja) 1989-01-14 1989-01-14 混成集積回路部品の構造
EP97200966A EP0789390B1 (en) 1989-01-14 1990-01-12 A method for producing a multilayer hybrid circuit
EP19900400092 EP0379404A3 (en) 1989-01-14 1990-01-12 A multilayer hybrid circuit
DE69034095T DE69034095T2 (de) 1989-01-14 1990-01-12 Verfahren zur Herstellung einer mehrschichtigen hybriden Schaltung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1007378A JP2790640B2 (ja) 1989-01-14 1989-01-14 混成集積回路部品の構造

Publications (2)

Publication Number Publication Date
JPH02187054A true JPH02187054A (ja) 1990-07-23
JP2790640B2 JP2790640B2 (ja) 1998-08-27

Family

ID=11664289

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Application Number Title Priority Date Filing Date
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Country Status (3)

Country Link
EP (2) EP0379404A3 (ja)
JP (1) JP2790640B2 (ja)
DE (1) DE69034095T2 (ja)

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US8592967B2 (en) 2009-01-28 2013-11-26 Hitachi Metals, Ltd. Semiconductor apparatus and power supply circuit
WO2015182114A1 (ja) * 2014-05-30 2015-12-03 パナソニックＩｐマネジメント株式会社 半導体装置、内蔵用キャパシタユニット、半導体実装体と、内蔵用キャパシタユニットの製造方法
JPWO2015182114A1 (ja) * 2014-05-30 2017-04-20 パナソニックＩｐマネジメント株式会社 半導体装置、内蔵用キャパシタユニット、半導体実装体と、内蔵用キャパシタユニットの製造方法

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EP0379404A2 (en) 1990-07-25
EP0379404A3 (en) 1993-03-31
DE69034095T2 (de) 2004-03-25
DE69034095D1 (de) 2003-09-18
EP0789390A2 (en) 1997-08-13
JP2790640B2 (ja) 1998-08-27
EP0789390B1 (en) 2003-08-13
EP0789390A3 (en) 1998-01-14

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