WO2010087407A1 - 半導体装置及び電源回路 - Google Patents
半導体装置及び電源回路 Download PDFInfo
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- WO2010087407A1 WO2010087407A1 PCT/JP2010/051150 JP2010051150W WO2010087407A1 WO 2010087407 A1 WO2010087407 A1 WO 2010087407A1 JP 2010051150 W JP2010051150 W JP 2010051150W WO 2010087407 A1 WO2010087407 A1 WO 2010087407A1
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- inductor
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- integrated circuit
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Definitions
- the present invention relates to a semiconductor device in which a semiconductor integrated circuit element including a switching transistor and a control circuit and an inductor are sealed with a resin, and particularly to a semiconductor device constituting a DC-DC converter and a power supply circuit including the semiconductor device.
- a secondary battery such as a lithium ion battery as a power source.
- Lithium-ion batteries usually generate a voltage of about 3.6 V (3.0 V to 4.2 V), so electronic devices are equipped with a DC-DC converter that steps down or boosts the operating voltage.
- DC-DC converters are also used in charging circuits.
- a DC-DC converter generally has a configuration in which a semiconductor integrated circuit element (active element) including a switching element and a control circuit, and passive elements such as an inductor and a capacitor are mounted on a printed circuit board.
- active element semiconductor integrated circuit element
- passive elements such as an inductor and a capacitor
- Japanese Patent Laid-Open No. 2005-183890 discloses a DC-DC converter in which a semiconductor integrated circuit 106, a capacitor 107, and the like are mounted on a laminate 150 including an inductor coil as shown in FIG.
- a plurality of external electrodes 111a for mounting mounting components such as the semiconductor integrated circuit 106 are formed on the top surface of the multilayer body 150, and a plurality of external electrodes 111b for connection to the mounting substrate are formed on the bottom surface.
- a first conductor pattern 109a connected to the external electrode 111a is formed across a plurality of nonmagnetic layers.
- a coil forming conductor pattern 108 is formed over a plurality of magnetic layers.
- a second conductor pattern 109b connected to the second external electrode 111b is formed across a plurality of nonmagnetic layers.
- a via hole 110 that penetrates the first wiring layer 101, the coil layer 103, and the second wiring layer 105 is formed in the outer peripheral area of the multilayer body 150.
- the semiconductor integrated circuit element 106 is connected to the lower surface pad via the via hole 110 of the multilayer body 150, the parasitic inductance generated by the via hole 110 causes the efficiency of the DC-DC converter to decrease and the output voltage to oscillate. May become unstable. Further, since it is packaged as the semiconductor integrated circuit element 106, it is more expensive than the bare chip type. Further, this DC-DC converter is inferior in heat dissipation of the semiconductor integrated circuit element 106.
- a semiconductor integrated circuit element 201 is mounted on the surface of a laminated body 209 containing an inductor or the like, and sealed with a mold resin 204 together with lead terminals 203 connected by bonding.
- a semiconductor device 200 is disclosed.
- the semiconductor device 200 has a DIP (dual-in-line package) type package structure, and the lead terminals 203 are connected to the side terminals 207 of the stacked body 209 and are connected to the semiconductor integrated circuit element 201 by bonding wires 202. ing.
- the heat of the semiconductor integrated circuit element 201 is transmitted to the stacked body 209, but since the whole is sealed with the mold resin, the heat is easily trapped.
- the lead terminal 203 is also reduced, so that the heat dissipation action of the lead terminal 203 is insufficient.
- the structure for molding the whole is not suitable for miniaturization.
- Japanese Patent Laid-Open No. 2007-81146 discloses a multilayer inductor 303 disposed on a support conductive plate 304 that is continuous with a lead terminal 305 and exposed on the outer surface, and a bare chip-shaped semiconductor disposed thereon.
- a QFN (Quad Flat Non-Leaded Package) type DC-DC converter 300 that includes an integrated circuit element 301 and is sealed with a mold resin 309 is disclosed.
- An electrode pad 302 formed on the upper surface of the semiconductor integrated circuit element 301 is connected to a lead terminal 305 by a bonding wire 308.
- the structure in which the multilayer inductor 303 is disposed on the support conductive plate 304 exposed on the outer surface is superior to the structure of Japanese Patent Laid-Open No.
- the DC-DC is equivalent to the support conductive plate 304.
- the converter 300 is also thickened. If the supporting conductive plate 304 is thinned to reduce the thickness of the DC-DC converter 300, the strength becomes insufficient, and if the inductor 303 is thinned, there arises a problem that the Q value of the inductor is lowered and the leakage magnetic flux is increased.
- an object of the present invention is to provide a semiconductor device that can be downsized and thinned without causing deterioration of characteristics or an increase in cost, has excellent heat dissipation, and can operate stably, and a power supply circuit using the semiconductor device. .
- a semiconductor device of the present invention is surrounded by a semiconductor integrated circuit element having a plurality of electrode pads, a plurality of first external terminals connected to the electrode pads of the semiconductor integrated circuit element, and the first external terminals.
- the semiconductor integrated circuit element is disposed on an upper surface of the inductor, and the inductor is disposed on the resin together with the first external terminal. It is exposed from the lower surface of the part.
- the inductor and the first external terminal are exposed from the bottom surface of the semiconductor device, it is not only advantageous in reducing the height, but also the inductor is brought into contact with the mounting substrate directly or through a heat dissipation material such as heat dissipation silicone. Then, the heat of the semiconductor integrated circuit element can be efficiently dissipated to the mounting substrate having a large heat capacity, and the temperature rise of the semiconductor integrated circuit element and the inductor can be suppressed, and the semiconductor device can be stably operated.
- the lower surface of the first external terminal and the lower surface of the inductor are substantially on the same plane. Since the difference in height is small, the entire semiconductor device can be thinned. By bringing the inductor and the mounting board into close contact with each other via a good thermal conductor or the like, the heat of the semiconductor integrated circuit element can be efficiently dissipated to the mounting board.
- a dummy terminal that is not electrically connected to the first external terminal is provided on the lower surface of the inductor. If the semiconductor device is not provided with a connection line between the second external terminal and the first external terminal but is connected by a connection line formed on the mounting substrate, the parasitic inductance can be reduced, and the semiconductor device and the mounting substrate The connection site increases and connection strength improves.
- the second external terminal also functions as a heat dissipation path. In this case, in order to ensure connection reliability with the mounting substrate, it is preferable to make the difference in height between the lower surface of the first external terminal and the lower surface of the inductor as small as possible.
- the parasitic inductance due to the connection wire is sufficiently smaller than the parasitic inductance due to the connection line.
- each terminal may extend to the side surface, but it is preferable not to straddle the upper and lower surfaces. If a terminal with low adhesion to the resin extends over the top and bottom surfaces because it has a plating film on the surface, the inductor may fall off the resin part or the airtightness of the resin may be lost. .
- the inductor has a rectangular plate shape and has a step or inclination on the side surface so that the area of the upper surface is larger than the lower surface. As a result, it is possible to prevent the sealing resin from dropping from the inductor or the loss of airtightness due to the sealing resin.
- adjacent first external terminals are connected via a capacitor, and the capacitor is sealed with a resin portion.
- the power supply circuit can be reduced in size.
- the first external terminal can be composed of a lead frame lead terminal or a resin substrate terminal.
- the lead terminal may have a shape having a lower end portion bent in a direction away from the lower surface of the inductor and an upper end portion bent toward the upper surface side of the inductor. With such a shape, it is possible to reduce the parasitic inductance due to the bonding wire, and to promote heat dissipation through the upper end connected to the inductor directly or via an internal terminal formed on the upper surface.
- the semiconductor integrated circuit element is flip-chip mounted on the upper end portion of the first external terminal extending on the upper surface of the inductor.
- a power supply according to the present invention includes the above-described semiconductor device.
- the parasitic inductance between the first external terminal connected to the mounting substrate and the semiconductor integrated circuit element can be reduced, the semiconductor device can be thinned, and the heat dissipation can be improved. Since the semiconductor integrated circuit element is disposed on the inductor, the mounting area of the semiconductor device can be reduced and the size can be reduced. In addition, the semiconductor device of the present invention is inexpensive because it can be manufactured in almost the same process as packaging of the semiconductor integrated circuit element. A power supply circuit including the semiconductor device of the present invention which is small and excellent in heat dissipation characteristics is small and excellent in conversion efficiency and the like.
- FIG. 2 (a) is a perspective view showing a bottom side of the semiconductor device of FIG.
- FIG. 2A is a perspective view showing the internal structure of the semiconductor device shown in FIG.
- FIG. 2 (a) is a plan view showing an internal structure of the semiconductor device shown in FIG. It is a top view which shows the lead frame used for manufacture of the semiconductor device of this invention.
- FIG. 4 (a) is a cross-sectional view showing the internal structure of the inductor shown in FIG. It is a perspective view which shows the external appearance of the other inductor used for the semiconductor device of this invention.
- FIG. 5 (a) is a cross-sectional view showing the internal structure of the inductor shown in FIG. It is a top view which shows the internal structure of the semiconductor device by the other Example of this invention. It is a perspective view which shows the internal structure of the semiconductor device by other Example of invention. It is a figure which shows an example of the power supply circuit which comprises the semiconductor device of this invention. It is a perspective view which shows the internal structure of the semiconductor device by other Example of this invention. It is a figure which shows the other example of the power supply circuit which comprises the semiconductor device of this invention. It is a figure which shows the further another example of the power supply circuit which comprises the semiconductor device of this invention. It is the schematic which shows the manufacturing process of the semiconductor device by one Example of this invention. FIG.
- FIG. 12 is a plan view showing a positional relationship among an inductor, a semiconductor integrated circuit element, and a lead frame in step C of FIG. It is a perspective view which shows the upper surface side of the semiconductor device by further another Example of this invention.
- FIG. 14 (a) is a perspective view showing the bottom side of the semiconductor device of FIG.
- FIG. 14 (a) is a perspective view showing the internal structure of the semiconductor device shown in FIG. It is sectional drawing which shows the conventional semiconductor device. It is a perspective view which shows the internal structure of another conventional semiconductor device. It is a perspective view which shows the internal structure of another conventional semiconductor device.
- a semiconductor device 1 includes a semiconductor integrated circuit element 30 having a plurality of electrode pads 31, and electrode pads of the semiconductor integrated circuit element 30.
- the semiconductor integrated circuit element 30 is disposed on the upper surface of the inductor 10, and the inductor 10 is exposed from the lower surface of the resin portion 25 together with the first external terminal 15a.
- the inductor 10 exposed on the bottom surface of the semiconductor device 1 is surrounded by a gap between the first external terminal 15a and the dummy terminal 15b disposed on the outer periphery of the bottom surface of the semiconductor device 1 so as to be exposed on the bottom surface and side surfaces. Sealed with mold resin 25.
- This configuration is a so-called leadless type (QFN: Quad Flat Non-Leaded Package) in which the first external terminal 15a and the dummy terminal 15b do not extend from the side surface of the semiconductor device 1, but of course, it is not limited and leads from the side surface May extend.
- the dummy terminal 15b is not electrically connected.
- the mold resin 25 may be any resin that has excellent adhesion, high glass transition temperature, low molding shrinkage and low elasticity, and little variation thereof.
- epoxy resin and phenol resin curing agent or biphenyl curing agent and A composition formed by mixing amorphous silica is exemplified.
- Specific examples of the epoxy resin include a cresol novolac epoxy resin, a phenol novolac epoxy resin, a biphenyl diepoxy resin, and a naphthol novolac epoxy resin.
- the mold resin 25 may contain a heat shrinkage adjusting filler, a flame retardant, and the like.
- the thermal conductivity of epoxy resin, etc. is about 0.2-1 W / m ⁇ K.
- Molding of the mold resin can be performed by a transmold method or a printing method.
- the printing method it is preferable to adopt a vacuum printing method or a differential pressure filling method in which printing is performed at a two-stage vacuum degree so that voids are not generated in a portion where it is difficult to fill the mold resin (for example, the lower side of the wire).
- Curing conditions can be appropriately set according to the mold resin, but heating at 150 to 250 ° C. for 1 to 5 hours is usually preferable.
- the first external terminal 15a and the dummy terminal 15b can be formed by the leads 55a and 55b of the lead frame 50 shown in FIG.
- the lead frame 50 has a plurality of leads 55a and 55b integrated by a frame 51 and a tie bar 52, and the leads 55a are connected to the electrode pads 31 of the semiconductor integrated circuit element 30 by bonding wires 35.
- a die pad for mounting a semiconductor integrated circuit element is supported by a suspension lead in a region surrounded by a plurality of leads.
- the die pad is not used, and the region surrounded by the leads is opened to the size of the inductor 10. is doing.
- the lead frame used in the present invention is made of a metal such as Fe-Ni alloy (for example, 42 alloy), copper, aluminum, gold, and the thickness and shape thereof are not particularly limited.
- a metal plate having a thickness of about 0.1 to 0.5 mm is preferably processed by pressing or etching into a predetermined shape and then plated with Ag, Au, Ni—Pd—Au, or Au—Pd.
- the thermal conductivity of 42 alloy is about 15 W / m ⁇ K
- the thermal conductivity of Cu, Ag, and aluminum is about 200 to 400 W / m ⁇ K.
- the lead spacing is set as appropriate in consideration of the number of terminals and wire bonding properties, but can be as narrow as 0.1 mm. In the case of a narrow pitch and a large number of leads, it is preferable to use a method in which a metal strip is coated with a photoresist and then etched into a predetermined pattern. Etching may be either a wet method or a dry method.
- an assembly tape is attached to the back surface of the lead frame 50, and the assembly tape side of the lead frame 50 is supported by a suction means or the like.
- the inductor 10 is arranged with high precision by a chip mounter. The assembly tape is not peeled until the resin sealing step, and holds the leads 55a and 55b that are finally separated, and prevents their surfaces from being covered with the mold resin.
- the assembly tape is supported by a heat resistant resin such as polyimide or polyethylene naphthalate.
- a heat resistant resin such as polyimide or polyethylene naphthalate.
- a film having an adhesive layer formed on one side of the film is preferable, and a polyimide having a glass transition temperature of 200 ° C. or higher is particularly preferable as a support film.
- the adhesive layer is preferably made of a thermoplastic resin having an ester group, an amide group, an imide group, an ether group, or a sulfone group.
- the bonding temperature to the lead frame is preferably 150 to 300 ° C.
- the assembly tape In order to prevent warping after the assembly tape is attached to the lead frame, the assembly tape preferably has a linear thermal expansion coefficient close to that of the lead frame.
- the thickness of the assembly tape is not limited, it is preferably 10 to 150 ⁇ m in consideration of warpage of the lead frame after application and ease of handling.
- the bare chip-shaped semiconductor integrated circuit element 30 is disposed on the inductor 10. An end portion of the bonding wire is connected to each electrode pad 31 of the semiconductor integrated circuit element 30 using an ultrasonic bonder device or the like.
- the bonding wire is mainly composed of a noble metal such as gold, silver or platinum, and may contain a transition metal such as copper or aluminum.
- the semiconductor integrated circuit element 30 is fixed to the inductor 10 by solder, conductive paste, conductive adhesive, DAF (Die (Attach Film) tape or the like. DAF is easy to handle and can reduce outgassing, preventing lead contamination and wire bonding.
- the low-profile inductor 10 uses, for example, a winding type in which a copper wire is wound around a ferrite magnetic core, and a low temperature co-fired ceramics LTCC (Low (Temperature Co-fired Ceramics), etc.
- LTCC Low (Temperature Co-fired Ceramics)
- laminated type in which a coil is formed by laminating, but a laminated inductor is preferable in consideration of a reduction in height and reduction of leakage magnetic flux.
- FIGS. 3 (a) and 3 (b) show an example of a multilayer inductor used in the present invention.
- this multilayer inductor 10 both ends of the coil constituted by the line pattern 18 in the multilayer body 11 are connected via via holes 19 to the second external terminal 16 exposed on the lower surface and the internal terminal 17 exposed on the upper surface.
- the second external terminal 16 is exposed from the lower surface of the mold resin 25, but the internal terminal 17 is covered with the mold resin 25.
- FIGS. 4 (a) and 4 (b) show other examples of the multilayer inductor used in the present invention.
- this multilayer inductor 10 both ends of the coil constituted by the line pattern 18 in the multilayer body 11 are connected via via holes 19 to second external terminals 16 and 16 exposed on the lower surface. Each second external terminal 16 is exposed from the lower surface of the mold resin 25.
- the second external terminal 16 on the bottom surface functions as a mounting terminal together with the first external terminal 15a and the dummy terminal 15b, the adhesion strength to the mounting board is increased, and even if the mounting board is twisted, bent, etc. There is no disconnection or damage to the multilayer inductor such as cracking. Further, heat is radiated from the semiconductor integrated circuit element 30 to the mounting substrate via the electrode having excellent thermal conductivity, so that the operation of the semiconductor device 1 is stabilized. In this state, the inductor 10 and the semiconductor integrated circuit element 30 are not connected, but can be appropriately connected by a connection line on the mounting substrate.
- the internal terminal 17 formed on the mounting side of the semiconductor integrated circuit element 30 can be connected to the first external terminal 15a by a bonding wire.
- the internal terminal 17 of the inductor 30 and the electrode pad 31 of the semiconductor integrated circuit element 30 are connected via a connection line (not shown) of the mounting substrate, but the internal terminal 17 and the electrode pad 31 are connected to each other by a bonding wire. You may connect directly.
- Each first external terminal 15a shown in FIG. 6 has a lower end portion 15ad bent in a direction away from the lower surface of the inductor 10, and an upper end portion 15au bent toward the upper surface side of the inductor 10.
- the upper end portion 15au of each first external terminal 15a is connected to the electrode pad 31 of the semiconductor integrated circuit element 30 by bonding wire, flip mounting or the like.
- the first external terminal 15a may also be connected to the internal terminal 17 or another electrode formed on the top surface of the inductor 10.
- the inductor 10 is preferably made of soft ferrite (Li ferrite, Mg ferrite or Ni ferrite). Li-based ferrite and Mg-based ferrite have small changes in magnetic properties due to stress, and Ni-based ferrite has small core loss. If Sn is added to Ni-based ferrite, the change in magnetic properties due to stress can be reduced.
- the soft ferrite used for the inductor 10 is appropriately selected in consideration of the conversion efficiency when a semiconductor device is used.
- the thermal conductivity of soft ferrite is generally about 5 W / m ⁇ k.
- a magnetic gap made of a non-magnetic material may be provided in the magnetic circuit of the inductor 10.
- a power supply circuit including the circuit shown in FIG. 7 can be configured as a semiconductor device.
- This power supply circuit is a step-down DC-DC converter.
- the semiconductor integrated circuit element 30 includes a switching element (MOS transistor), a control circuit for alternately turning it on and off, and an inverter.
- the input capacitor Cin provided for stabilizing the input voltage Vin during transition and preventing voltage spikes can be omitted.
- a smoothing circuit (filter circuit) for outputting the DC voltage Vout includes an inductor 10 that stores and discharges current energy and an output capacitor Cout that stores and discharges voltage energy.
- Vin, Vout, GND, SW, EN, and Mode are added to the first external terminal 15a, respectively, but the terminals for ON / OFF control of the switching elements are omitted.
- Vin and Vout are connected to an input terminal and an output terminal of the semiconductor integrated circuit element 30, respectively.
- GND is connected to the ground terminal of the semiconductor integrated circuit element 30.
- EN is connected to the output ON / OFF control terminal of the semiconductor integrated circuit element 30.
- Mode is connected to the output voltage control terminal of the semiconductor integrated circuit element 30.
- an input capacitor Cin and an output capacitor Cout may be built in the power supply circuit so as to be disposed between the adjacent first external terminals 15a and 15a.
- the illustrated circuit is a step-down type, the present invention can of course be applied to a step-up type or other circuit configurations.
- FIG. 9 shows a power supply circuit using a multi-output power management IC as a semiconductor integrated circuit element.
- This power supply circuit receives a control signal from the host HOST, turns on / off multiple switching elements, converts the input voltage to supply DC power to the output terminals Vout1 and Vout2, and also outputs DC power from the four series regulator outputs.
- Supply power Vout3 ⁇ Vout6 Since the inductor 10 in this power supply circuit is composed of an inductor array having two inductor coils, the number of second external terminals 16 and internal terminals 17 is four at the maximum.
- FIG. 10 shows a power supply circuit using a secondary battery charger IC as a semiconductor integrated circuit element.
- This power supply circuit receives a control signal from the host HOST, turns on / off the plurality of switching elements, converts the input voltage, and supplies DC power to the output terminal Vout.
- the charging current to the secondary battery (lithium ion battery) is detected from both ends of the charging current detection resistor Rsen connected in series to the inductor 10, and the charging current is optimally controlled according to the output voltage by the control signal of the host HOST. To do.
- FIG. 11 shows an example of a method for manufacturing the semiconductor device of the present invention having the structure shown in FIGS. 1 (a) to 1 (d).
- a lead frame 50 shown in FIG. 2 was used for assembling the semiconductor device.
- the lead frame 50 was manufactured by etching a copper alloy sheet having a thickness of 0.15 mm and performing Ag plating. In order to improve solderability, Sn-Bi plating was applied to the back surface of the lead frame 50.
- the lead frame 50 has a plurality of tie bars 52 extending vertically and horizontally inside the frame 51, and the inside of the frame 51 is divided into a plurality of (15 in this embodiment) sections forming a semiconductor device.
- leads 55a and 55b extend integrally from the frame 51 and the tie bar 52, and the free ends of the leads 55a and 55b do not reach the center of each region, and form an opening 56.
- Each lead 55a, 55b extends linearly with the same width and length, but the width and length may be different.
- the width of each lead may be partially different so that the connection portion with the bonding wire becomes wider.
- the leads 55a and 55b may extend in different directions such as in a radial manner.
- the leads 55a and 55b may be partially bent or bent in the horizontal direction or the vertical direction.
- the frame 51 may be a long tape.
- An assembly tape 60 consisting of a support film made of a polyimide film with a thickness of 100 ⁇ m and an adhesive layer made of an aromatic polyether amide imide with a thickness of 20 ⁇ m is pasted on one surface of the lead frame 50 at 200 ° C. and 5 mm Bonding was performed by applying pressure for 10 seconds (step A).
- the multilayer inductor 10 having the configuration shown in FIGS. 4A and 4B was attached to the assembly tape 60 exposed in the region 56 surrounded by the leads 55a and 55b of the lead frame 50 (process B).
- the outer dimensions of the multilayer inductor 10 are 1.5 mm ⁇ 1.5 mm ⁇ 0.55 mm, both ends of the built-in coil are connected to the second external terminals 16, 16 on the lower surface, and the magnetic core is Ni containing Sn as a subcomponent Made of ferrite.
- the conditions for applying the multilayer inductor 10 to the assembly tape 60 were the pressurization for 10 seconds at 200 ° C. and 5 MPa as in the case of the lead frame 50.
- the bonding conditions can be appropriately changed according to the bonding state.
- a semiconductor integrated circuit element 31 having an outer dimension of 1.1 mm ⁇ 0.7 mm ⁇ 0.1 mm and a DAF tape (not shown) with a thickness of 25 ⁇ m adhered to the bottom surface of the inductor 10 was fixed.
- the semiconductor integrated circuit element 31 is fixed to the mounting electrode formed on the upper surface of the inductor 10 with a conductive paste such as silver paste, it is preferably heated at 120 to 200 ° C. for 30 to 60 minutes.
- the gold wire 35 was brought into contact with the electrode pad 31 of the semiconductor integrated circuit element 30 and the leads 55a and 55b of the lead frame 50 and heated to 250 ° C. for 5 minutes for wire bonding (step C).
- the upper electrode pad 31a of the semiconductor integrated circuit element 30 is connected to the upper lead 55a
- the lower electrode pad 31b is connected to the lower lead 55b.
- the two leads 55b and 55b located on the left and right of the inductor 10 were not connected to the electrode pad 31, and were used as terminals NC for improving the adhesion strength with the mounting board.
- the terminal NC may be connected to the electrode pad 31 and the second external terminal 16 and internal terminal 17 of the inductor 10.
- a liquid phenol novolac type epoxy resin sealing material as a mold resin is printed on a plurality of semiconductor integrated circuit elements 30 and the inductor 10 to a cured thickness of 1.0 mm, cured by heating at 250 ° C. for 2 hours, and then collectively sealed. (Process D). Next, the assembly tape 60 was peeled off while being heated to 100 to 200 ° C. so that the adhesive (resin layer) of the assembly tape 60 did not remain on the lead frame 50, the inductor 10 and the mold resin 25 (step E). If the resin layer remains, it is removed with a solvent.
- the sealed lead frame 50 was divided for each semiconductor integrated circuit element 30 with a cutting saw, and a semiconductor device having an outer dimension of 2.1 mm ⁇ 2.1 mm ⁇ 1.0 mm was manufactured (step F).
- the lead frame 50 can be cut by using a water jet or a laser instead of the cutting saw. Further, the order of the process E and the process F may be switched. In that case, by dividing the assembly tape 60 so as not to be cut, the semiconductor device 1 can be held in the assembly tape 60, and the handling becomes easy.
- Comparative Example 1 The external dimensions are 2.1 mm as in Example 1 except that a lead frame having a long lead is used to overlap the second external terminal 16 of the inductor 10 and the lead and the second external terminal 16 are connected by solder. A semiconductor device of ⁇ 2.1 mm ⁇ 1.15 mm was obtained. This semiconductor device was thicker than that of Example 1 by the amount of the lead frame. Further, since the lower surface of the inductor 10 was almost covered with the mold resin 25, the heat dissipation was inferior.
- Example 1 and Comparative Example 1 After mounting 15 semiconductor devices of Example 1 and Comparative Example 1 on the center of the test printed circuit board, and attaching eutectic solder to the land formed on the printed circuit board and the external terminals of the semiconductor device, an autograph (AG Load was applied 5 times from the back side of the center of the printed circuit board until the displacement became 1.0 mm, and a three-point bending test was performed. As a result, the semiconductor devices of Example 1 and Comparative Example 1 did not fall off the printed circuit board, and the external terminals did not come off the land. However, some of the semiconductor devices of Comparative Example 1 were inductors and semiconductor integrated circuits. Some devices had cracks.
- Example 2 A semiconductor whose outer dimensions are 2.1 mm ⁇ 2.1 mm ⁇ 0.9 mm shown in FIGS. 13 (a) to 13 (c) in the same manner as in Example 1 except that the lead frame 50 not having the lead 55b serving as the terminal NC is used. A device was made. Since the mounting area of the inductor 10 is expanded by the absence of the terminal NC, the inductor 10 that is larger in plan than the first embodiment can be used. Since the magnetic path area is also expanded, an inductor thinner than that of the first embodiment can be used if the inductance is the same. Since the outer dimension of the inductor 10 used in this example is 2.1 mm ⁇ 1.5 mm ⁇ 0.45 mm, the two opposite sides of the inductor 10 are exposed from the mold resin 25. This semiconductor device had no difference in electrical characteristics from that of Example 1, and was as thin as the inductor 10. In the three-point bending test, the inductor 10 and the semiconductor integrated circuit element 30 were not cracked.
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Abstract
Description
図11は、図1(a)~図1(d) に示す構造を有する本発明の半導体装置を製造する方法の一例を示す。半導体装置の組立てに、図2に示すリードフレーム50を用いた。リードフレーム50は、厚さ0.15 mmの銅合金シートをエッチング加工し、Agめっきすることにより作製した。半田付け性を向上させるため、リードフレーム50の裏面にSn-Biめっきを施した。
インダクタ10の第二の外部端子16と重なるように長いリードを有するリードフレームを用い、リードと第二の外部端子16とを半田で接続した以外実施例1と同様にして、外形寸法が2.1 mm×2.1 mm×1.15 mmの半導体装置を得た。この半導体装置は実施例1のものよりリードフレームの分だけ厚かった。またインダクタ10の下面がほとんどモールド樹脂25で覆われたので、放熱性に劣った。
端子NCとなるリード55bを備えないリードフレーム50を用いた以外実施例1と同様にして、図13(a)~図13(c) に示す外形寸法が2.1 mm×2.1 mm×0.9 mmの半導体装置を作製した。端子NCがない分、インダクタ10の実装領域が拡張されるので、実施例1より平面的に大きなインダクタ10を使用できる。磁路面積も拡張されるので、同じインダクタンスであれば実施例1より薄いインダクタを用いることができる。本実施例で用いたインダクタ10の外形寸法は2.1 mm×1.5 mm×0.45 mmであるので、インダクタ10の対向する2辺はモールド樹脂25から露出した。この半導体装置は実施例1のものと電気的特性に差がなく、インダクタ10の分だけ薄かった。3点曲げ試験でもインダクタ10及び半導体集積回路素子30にクラックが生じなかった。
Claims (11)
- 複数の電極パッドを有する半導体集積回路素子と、前記半導体集積回路素子の電極パッドに接続された複数の第一の外部端子と、前記第一の外部端子に囲まれた領域内に配置されたインダクタと、それらを封止する樹脂部とを備え、前記半導体集積回路素子は前記インダクタの上面に配置されており、前記インダクタは前記第一の外部端子とともに前記樹脂部の下面から露出していることを特徴とする半導体装置。
- 請求項1に記載の半導体装置において、前記第一の外部端子の下面と前記インダクタの下面とが実質的に同一平面上に存在することを特徴とする半導体装置。
- 請求項1又は2に記載の半導体装置において、前記インダクタの下面に前記第一の外部端子と電気的に接続されていないダミー端子を備えていることを特徴とする半導体装置。
- 請求項1~3のいずれかに記載の半導体装置において、前記インダクタの上面に内部端子を備え、前記内部端子と前記第一の外部端子とはワイヤで接続されていることを特徴とする半導体装置。
- 請求項1~4のいずれかに記載の半導体装置において、前記インダクタは矩形板状であり、その側面に段差又は傾斜を持たせて上面の面積を下面より大きくしたことを特徴とする半導体装置。
- 請求項1~5のいずれかに記載の半導体装置において、隣り合う第一の外部端子間に接続されたコンデンサを備え、前記コンデンサは前記樹脂部で封止されていることを特徴とする半導体装置。
- 請求項1~6のいずれかに記載の半導体装置において、前記第一の外部端子はリードフレームのリード端子で構成されていることを特徴とする半導体装置。
- 請求項7に記載の半導体装置において、前記第一の外部端子は前記インダクタの下面から離れる方向に折り曲げられた下端部と、インダクタの上面側に折り曲げられた上端部とを有することを特徴とする半導体装置。
- 請求項8に記載の半導体装置において、第一の外部端子の上端部に前記半導体集積回路素子がフリップチップ実装されていることを特徴とする半導体装置。
- 請求項1~6のいずれかに記載の半導体装置において、前記第一の外部端子が樹脂基板の端子部で構成されていることを特徴とする半導体装置。
- 請求項1~10のいずれかに記載の半導体装置を具備することを特徴とする電源回路。
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EP10735872.3A EP2393113A4 (en) | 2009-01-28 | 2010-01-28 | SEMICONDUCTOR DEVICE AND POWER CIRCUIT |
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US20140292462A1 (en) * | 2013-03-28 | 2014-10-02 | Inpaq Technology Co., Ltd. | Power inductor and method for fabricating the same |
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US20110284989A1 (en) | 2011-11-24 |
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US8592967B2 (en) | 2013-11-26 |
JPWO2010087407A1 (ja) | 2012-08-02 |
JP5614286B2 (ja) | 2014-10-29 |
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