JP7731879B2 - 半導体装置、電子機器 - Google Patents

半導体装置、電子機器

Info

Publication number
JP7731879B2
JP7731879B2 JP2022530087A JP2022530087A JP7731879B2 JP 7731879 B2 JP7731879 B2 JP 7731879B2 JP 2022530087 A JP2022530087 A JP 2022530087A JP 2022530087 A JP2022530087 A JP 2022530087A JP 7731879 B2 JP7731879 B2 JP 7731879B2
Authority
JP
Japan
Prior art keywords
semiconductor device
sub
power supply
contact
supply line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2022530087A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2021251081A5 (https=
JPWO2021251081A1 (https=
Inventor
修平 ▲高▼際
博司 古谷
健 清家
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Publication of JPWO2021251081A1 publication Critical patent/JPWO2021251081A1/ja
Publication of JPWO2021251081A5 publication Critical patent/JPWO2021251081A5/ja
Application granted granted Critical
Publication of JP7731879B2 publication Critical patent/JP7731879B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/645—Combinations of only lateral BJTs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
    • H03F3/45085—Long tailed pairs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/67—Complementary BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45528—Indexing scheme relating to differential amplifiers the FBC comprising one or more passive resistors and being coupled between the LC and the IC
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45612—Indexing scheme relating to differential amplifiers the IC comprising one or more input source followers as input stages in the IC
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs
    • H10D10/421—Vertical BJTs having both emitter-base and base-collector junctions ending at the same surface of the body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/60—Lateral BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/63—Combinations of vertical and lateral BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2022530087A 2020-06-08 2021-05-19 半導体装置、電子機器 Active JP7731879B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2020099164 2020-06-08
JP2020099164 2020-06-08
PCT/JP2021/018899 WO2021251081A1 (ja) 2020-06-08 2021-05-19 半導体装置、電子機器

Publications (3)

Publication Number Publication Date
JPWO2021251081A1 JPWO2021251081A1 (https=) 2021-12-16
JPWO2021251081A5 JPWO2021251081A5 (https=) 2023-02-20
JP7731879B2 true JP7731879B2 (ja) 2025-09-01

Family

ID=78847227

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022530087A Active JP7731879B2 (ja) 2020-06-08 2021-05-19 半導体装置、電子機器

Country Status (5)

Country Link
US (1) US20230223403A1 (https=)
JP (1) JP7731879B2 (https=)
CN (1) CN115702500A (https=)
DE (1) DE112021002303B4 (https=)
WO (1) WO2021251081A1 (https=)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000114461A (ja) 1998-09-29 2000-04-21 Sanyo Electric Co Ltd 半導体集積回路装置
JP2002246553A (ja) 2001-02-16 2002-08-30 Matsushita Electric Ind Co Ltd 半導体集積回路のノイズ低減装置
JP2005039320A (ja) 2003-07-15 2005-02-10 Renesas Technology Corp 半導体素子及び高周波電力増幅装置
JP2008071818A (ja) 2006-09-12 2008-03-27 Nec Electronics Corp 半導体装置
JP2008112857A (ja) 2006-10-30 2008-05-15 Nec Electronics Corp 半導体集積回路装置
JP2008193019A (ja) 2007-02-08 2008-08-21 Matsushita Electric Ind Co Ltd 半導体集積回路装置
JP2012009841A (ja) 2010-05-21 2012-01-12 Semiconductor Energy Lab Co Ltd 半導体素子、及び半導体装置
WO2019039245A1 (ja) 2017-08-22 2019-02-28 ローム株式会社 オペアンプ
JP2020004936A (ja) 2018-07-02 2020-01-09 株式会社デンソー 半導体装置およびその製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08115985A (ja) * 1994-10-17 1996-05-07 Nec Corp 低雑音の半導体集積回路
JP4513575B2 (ja) * 2005-01-12 2010-07-28 三菱電機株式会社 保持解放機構
JP5724934B2 (ja) 2011-07-05 2015-05-27 株式会社デンソー 半導体装置
US10608168B2 (en) * 2017-10-04 2020-03-31 Allegro Microsystems, Llc Isolated hall effect element with improved electro-magnetic isolation
JP7308595B2 (ja) * 2018-07-02 2023-07-14 Ｔｉａｎｍａ Ｊａｐａｎ株式会社 イメージセンサ

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000114461A (ja) 1998-09-29 2000-04-21 Sanyo Electric Co Ltd 半導体集積回路装置
JP2002246553A (ja) 2001-02-16 2002-08-30 Matsushita Electric Ind Co Ltd 半導体集積回路のノイズ低減装置
JP2005039320A (ja) 2003-07-15 2005-02-10 Renesas Technology Corp 半導体素子及び高周波電力増幅装置
JP2008071818A (ja) 2006-09-12 2008-03-27 Nec Electronics Corp 半導体装置
JP2008112857A (ja) 2006-10-30 2008-05-15 Nec Electronics Corp 半導体集積回路装置
JP2008193019A (ja) 2007-02-08 2008-08-21 Matsushita Electric Ind Co Ltd 半導体集積回路装置
JP2012009841A (ja) 2010-05-21 2012-01-12 Semiconductor Energy Lab Co Ltd 半導体素子、及び半導体装置
WO2019039245A1 (ja) 2017-08-22 2019-02-28 ローム株式会社 オペアンプ
JP2020004936A (ja) 2018-07-02 2020-01-09 株式会社デンソー 半導体装置およびその製造方法

Also Published As

Publication number Publication date
DE112021002303T5 (de) 2023-03-16
WO2021251081A1 (ja) 2021-12-16
CN115702500A (zh) 2023-02-14
US20230223403A1 (en) 2023-07-13
JPWO2021251081A1 (https=) 2021-12-16
DE112021002303B4 (de) 2023-09-21

Similar Documents

Publication Publication Date Title
US11528001B2 (en) Operational amplifier
CN110021595B (zh) 半导体装置
JP7731879B2 (ja) 半導体装置、電子機器
US5160997A (en) Semiconductor integrated circuit with shield electrodes for protecting the interconnection lines from undesirable radiation
JP4381592B2 (ja) 半導体装置
TWI747145B (zh) 半導體裝置及放大器模組
JP2724193B2 (ja) 半導体装置
WO1995022839A1 (en) Packaged integrated circuit with reduced electromagnetic interference
CN111278265B (zh) 具有隔离屏蔽结构的信号走线
JPH08316330A (ja) 半導体集積回路のレイアウト方法
JP4279034B2 (ja) 半導体装置
JPH0251253A (ja) 半導体集積回路
CN112703593A (zh) 布线基板
CN121332236A (zh) 线缆连接器
CN112117256A (zh) 半导体装置
JP2004119506A (ja) ハイブリッド集積モジュール
JPH03231444A (ja) 半導体装置
JPH1031837A (ja) 光学式情報記録再生装置
JP2008198694A (ja) 受光装置
JPH02170541A (ja) 横方向トランジスタ
JPH0523067B2 (https=)

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221028

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20240319

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20250513

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20250707

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20250729

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20250820

R150 Certificate of patent or registration of utility model

Ref document number: 7731879

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150