JP7219521B2 - プラチナパターニングのための犠牲層 - Google Patents

プラチナパターニングのための犠牲層 Download PDF

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JP7219521B2
JP7219521B2 JP2019539221A JP2019539221A JP7219521B2 JP 7219521 B2 JP7219521 B2 JP 7219521B2 JP 2019539221 A JP2019539221 A JP 2019539221A JP 2019539221 A JP2019539221 A JP 2019539221A JP 7219521 B2 JP7219521 B2 JP 7219521B2
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layer
platinum
sacrificial layer
sidewall surfaces
sacrificial
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Japanese (ja)
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JP2020516050A (ja
JP2020516050A5 (https=
Inventor
マイヤー サバスティアン
リンク ヘルムト
アレクサンダー シャハトシュナイダー カイ
メッツ フロマンド
シュミドペーター マリオ
モレイラ ハビエル
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テキサス インスツルメンツ インコーポレイテッド
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/054Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by selectively removing parts thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/44Physical vapour deposition [PVD]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/71Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/202Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials for lift-off processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/403Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials for lift-off processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/031Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44Conductive materials thereof
    • H10W20/4403Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4432Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Micromachines (AREA)
JP2019539221A 2017-01-19 2018-01-19 プラチナパターニングのための犠牲層 Active JP7219521B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762448110P 2017-01-19 2017-01-19
US62/448,110 2017-01-19
US15/658,039 2017-07-24
US15/658,039 US10297497B2 (en) 2017-01-19 2017-07-24 Sacrificial layer for platinum patterning
PCT/US2018/014531 WO2018136802A1 (en) 2017-01-19 2018-01-19 Sacrificial layer for platinum patterning

Publications (3)

Publication Number Publication Date
JP2020516050A JP2020516050A (ja) 2020-05-28
JP2020516050A5 JP2020516050A5 (https=) 2021-02-25
JP7219521B2 true JP7219521B2 (ja) 2023-02-08

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019539221A Active JP7219521B2 (ja) 2017-01-19 2018-01-19 プラチナパターニングのための犠牲層

Country Status (5)

Country Link
US (1) US10297497B2 (https=)
EP (1) EP3571711B1 (https=)
JP (1) JP7219521B2 (https=)
CN (1) CN110337710B (https=)
WO (1) WO2018136802A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11011381B2 (en) 2018-07-27 2021-05-18 Texas Instruments Incorporated Patterning platinum by alloying and etching platinum alloy
CN111945128A (zh) * 2020-08-18 2020-11-17 江苏能华微电子科技发展有限公司 一种提高铂与衬底黏附性的方法及其产品
US12607594B2 (en) 2020-09-03 2026-04-21 Texas Instruments Incorporated ISFET biosensor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000091270A (ja) 1998-09-16 2000-03-31 Nec Corp 強誘電体容量で用いる電極のスパッタ成長方法
JP2003258327A (ja) 2001-08-03 2003-09-12 Yamaha Corp 貴金属薄膜パターンの形成方法
JP2015065280A (ja) 2013-09-25 2015-04-09 日亜化学工業株式会社 金属膜の形成方法及び発光素子の製造方法

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US4497684A (en) * 1983-02-22 1985-02-05 Amdahl Corporation Lift-off process for depositing metal on a substrate
JPS59165425A (ja) * 1983-03-10 1984-09-18 Matsushita Electric Ind Co Ltd パタ−ン形成方法
JPH065717A (ja) * 1992-06-19 1994-01-14 Toshiba Corp 電極へのオーム性接続金属層の形成方法
JPH07130702A (ja) * 1993-11-08 1995-05-19 Fujitsu Ltd 白金又はパラジウムよりなる金属膜のパターニング方法
JPH07273280A (ja) * 1994-03-29 1995-10-20 Tokin Corp 薄膜パターンの形成方法
US5914507A (en) 1994-05-11 1999-06-22 Regents Of The University Of Minnesota PZT microdevice
KR100224660B1 (ko) 1996-06-17 1999-10-15 윤종용 백금-폴리실리콘 게이트 형성방법
JP3481415B2 (ja) * 1997-03-19 2003-12-22 富士通株式会社 半導体装置及びその製造方法
US6218297B1 (en) * 1998-09-03 2001-04-17 Micron Technology, Inc. Patterning conductive metal layers and methods using same
US6956274B2 (en) * 2002-01-11 2005-10-18 Analog Devices, Inc. TiW platinum interconnect and method of making the same
US7829215B2 (en) 2005-08-29 2010-11-09 University Of South Florida Surface micromachined electrolyte-cavities for use in micro-aluminum galvanic cells
CN100479102C (zh) * 2006-08-29 2009-04-15 中国科学院声学研究所 一种图形化铂/钛金属薄膜的剥离制备方法
US20080124823A1 (en) * 2006-11-24 2008-05-29 United Microdisplay Optronics Corp. Method of fabricating patterned layer using lift-off process
KR101045090B1 (ko) * 2008-11-13 2011-06-29 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성방법
RU2426193C1 (ru) 2010-05-05 2011-08-10 Федеральное государственное бюджетное учреждение "Национальный исследовательский центр "Курчатовский институт" Способ нанесения платиновых слоев на подложку
MY151464A (en) * 2010-12-09 2014-05-30 Mimos Berhad A method of fabricating a semiconductor device
US9006105B2 (en) 2013-07-30 2015-04-14 United Microelectronics Corp. Method of patterning platinum layer
US9903763B2 (en) 2013-09-27 2018-02-27 Robert Bosch Gmbh Titanium nitride for MEMS bolometers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000091270A (ja) 1998-09-16 2000-03-31 Nec Corp 強誘電体容量で用いる電極のスパッタ成長方法
JP2003258327A (ja) 2001-08-03 2003-09-12 Yamaha Corp 貴金属薄膜パターンの形成方法
JP2015065280A (ja) 2013-09-25 2015-04-09 日亜化学工業株式会社 金属膜の形成方法及び発光素子の製造方法

Also Published As

Publication number Publication date
EP3571711B1 (en) 2024-05-22
US10297497B2 (en) 2019-05-21
US20180204767A1 (en) 2018-07-19
EP3571711A1 (en) 2019-11-27
CN110337710B (zh) 2023-12-26
EP3571711A4 (en) 2020-09-09
JP2020516050A (ja) 2020-05-28
WO2018136802A1 (en) 2018-07-26
CN110337710A (zh) 2019-10-15

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