JP7219521B2 - プラチナパターニングのための犠牲層 - Google Patents

プラチナパターニングのための犠牲層 Download PDF

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JP7219521B2
JP7219521B2 JP2019539221A JP2019539221A JP7219521B2 JP 7219521 B2 JP7219521 B2 JP 7219521B2 JP 2019539221 A JP2019539221 A JP 2019539221A JP 2019539221 A JP2019539221 A JP 2019539221A JP 7219521 B2 JP7219521 B2 JP 7219521B2
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layer
platinum
sacrificial layer
sidewall surfaces
sacrificial
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JP2020516050A (ja
JP2020516050A5 (enExample
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マイヤー サバスティアン
リンク ヘルムト
アレクサンダー シャハトシュナイダー カイ
メッツ フロマンド
シュミドペーター マリオ
モレイラ ハビエル
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テキサス インスツルメンツ インコーポレイテッド
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0331—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Micromachines (AREA)
JP2019539221A 2017-01-19 2018-01-19 プラチナパターニングのための犠牲層 Active JP7219521B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201762448110P 2017-01-19 2017-01-19
US62/448,110 2017-01-19
US15/658,039 2017-07-24
US15/658,039 US10297497B2 (en) 2017-01-19 2017-07-24 Sacrificial layer for platinum patterning
PCT/US2018/014531 WO2018136802A1 (en) 2017-01-19 2018-01-19 Sacrificial layer for platinum patterning

Publications (3)

Publication Number Publication Date
JP2020516050A JP2020516050A (ja) 2020-05-28
JP2020516050A5 JP2020516050A5 (enExample) 2021-02-25
JP7219521B2 true JP7219521B2 (ja) 2023-02-08

Family

ID=62841661

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Application Number Title Priority Date Filing Date
JP2019539221A Active JP7219521B2 (ja) 2017-01-19 2018-01-19 プラチナパターニングのための犠牲層

Country Status (5)

Country Link
US (1) US10297497B2 (enExample)
EP (1) EP3571711B1 (enExample)
JP (1) JP7219521B2 (enExample)
CN (1) CN110337710B (enExample)
WO (1) WO2018136802A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11011381B2 (en) 2018-07-27 2021-05-18 Texas Instruments Incorporated Patterning platinum by alloying and etching platinum alloy
CN111945128A (zh) * 2020-08-18 2020-11-17 江苏能华微电子科技发展有限公司 一种提高铂与衬底黏附性的方法及其产品

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000091270A (ja) 1998-09-16 2000-03-31 Nec Corp 強誘電体容量で用いる電極のスパッタ成長方法
JP2003258327A (ja) 2001-08-03 2003-09-12 Yamaha Corp 貴金属薄膜パターンの形成方法
JP2015065280A (ja) 2013-09-25 2015-04-09 日亜化学工業株式会社 金属膜の形成方法及び発光素子の製造方法

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US4497684A (en) * 1983-02-22 1985-02-05 Amdahl Corporation Lift-off process for depositing metal on a substrate
JPS59165425A (ja) * 1983-03-10 1984-09-18 Matsushita Electric Ind Co Ltd パタ−ン形成方法
JPH065717A (ja) * 1992-06-19 1994-01-14 Toshiba Corp 電極へのオーム性接続金属層の形成方法
JPH07130702A (ja) * 1993-11-08 1995-05-19 Fujitsu Ltd 白金又はパラジウムよりなる金属膜のパターニング方法
JPH07273280A (ja) * 1994-03-29 1995-10-20 Tokin Corp 薄膜パターンの形成方法
US5914507A (en) 1994-05-11 1999-06-22 Regents Of The University Of Minnesota PZT microdevice
KR100224660B1 (ko) 1996-06-17 1999-10-15 윤종용 백금-폴리실리콘 게이트 형성방법
JP3481415B2 (ja) * 1997-03-19 2003-12-22 富士通株式会社 半導体装置及びその製造方法
US6218297B1 (en) * 1998-09-03 2001-04-17 Micron Technology, Inc. Patterning conductive metal layers and methods using same
US6956274B2 (en) * 2002-01-11 2005-10-18 Analog Devices, Inc. TiW platinum interconnect and method of making the same
US7829215B2 (en) 2005-08-29 2010-11-09 University Of South Florida Surface micromachined electrolyte-cavities for use in micro-aluminum galvanic cells
CN100479102C (zh) * 2006-08-29 2009-04-15 中国科学院声学研究所 一种图形化铂/钛金属薄膜的剥离制备方法
US20080124823A1 (en) * 2006-11-24 2008-05-29 United Microdisplay Optronics Corp. Method of fabricating patterned layer using lift-off process
KR101045090B1 (ko) * 2008-11-13 2011-06-29 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성방법
RU2426193C1 (ru) 2010-05-05 2011-08-10 Федеральное государственное бюджетное учреждение "Национальный исследовательский центр "Курчатовский институт" Способ нанесения платиновых слоев на подложку
MY151464A (en) * 2010-12-09 2014-05-30 Mimos Berhad A method of fabricating a semiconductor device
US9006105B2 (en) 2013-07-30 2015-04-14 United Microelectronics Corp. Method of patterning platinum layer
WO2015048424A1 (en) 2013-09-27 2015-04-02 Robert Bosch Gmbh Titanium nitride for mems bolometers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000091270A (ja) 1998-09-16 2000-03-31 Nec Corp 強誘電体容量で用いる電極のスパッタ成長方法
JP2003258327A (ja) 2001-08-03 2003-09-12 Yamaha Corp 貴金属薄膜パターンの形成方法
JP2015065280A (ja) 2013-09-25 2015-04-09 日亜化学工業株式会社 金属膜の形成方法及び発光素子の製造方法

Also Published As

Publication number Publication date
EP3571711A4 (en) 2020-09-09
EP3571711A1 (en) 2019-11-27
JP2020516050A (ja) 2020-05-28
US10297497B2 (en) 2019-05-21
CN110337710A (zh) 2019-10-15
CN110337710B (zh) 2023-12-26
US20180204767A1 (en) 2018-07-19
WO2018136802A1 (en) 2018-07-26
EP3571711B1 (en) 2024-05-22

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