JP7207859B2 - ３次元半導体メモリ装置及びその製造方法 - Google Patents

３次元半導体メモリ装置及びその製造方法 Download PDF

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Publication number
JP7207859B2
JP7207859B2 JP2018074160A JP2018074160A JP7207859B2 JP 7207859 B2 JP7207859 B2 JP 7207859B2 JP 2018074160 A JP2018074160 A JP 2018074160A JP 2018074160 A JP2018074160 A JP 2018074160A JP 7207859 B2 JP7207859 B2 JP 7207859B2
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vertical
pattern
semiconductor
semiconductor pattern
memory device
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JP2018182320A (ja
JP2018182320A5 (enExample
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昭 賢 李
善 一 沈
載 悳 李
在 薫 張
智 勳 韓
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/693—Vertical IGFETs having charge trapping gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H10D84/0133—Manufacturing common source or drain regions between multiple IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
JP2018074160A 2017-04-10 2018-04-06 ３次元半導体メモリ装置及びその製造方法 Active JP7207859B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020170046229A KR102332346B1 (ko) 2017-04-10 2017-04-10 3차원 반도체 메모리 장치 및 그의 제조 방법
KR10-2017-0046229 2017-04-10

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JP2018182320A JP2018182320A (ja) 2018-11-15
JP2018182320A5 JP2018182320A5 (enExample) 2021-04-22
JP7207859B2 true JP7207859B2 (ja) 2023-01-18

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US (1) US10396088B2 (enExample)
JP (1) JP7207859B2 (enExample)
KR (1) KR102332346B1 (enExample)
CN (1) CN108695339B (enExample)

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JP2020017572A (ja) * 2018-07-23 2020-01-30 キオクシア株式会社 半導体メモリ及び半導体メモリの製造方法
CN110121778B (zh) * 2019-03-04 2020-08-25 长江存储科技有限责任公司 三维存储器件
WO2020177049A1 (en) 2019-03-04 2020-09-10 Yangtze Memory Technologies Co., Ltd. Methods for forming three-dimensional memory devices
KR102778239B1 (ko) * 2019-04-25 2025-03-10 삼성전자주식회사 수직형 반도체 소자
KR102923273B1 (ko) 2019-06-27 2026-02-04 양쯔 메모리 테크놀로지스 씨오., 엘티디. 신규 3d nand 메모리 디바이스 및 그 형성 방법
KR102728797B1 (ko) * 2019-07-31 2024-11-11 삼성전자주식회사 반도체 장치 및 이의 동작 방법
KR102801211B1 (ko) * 2019-10-29 2025-04-29 삼성전자주식회사 돌출한 비아 라이너 층을 갖는 관통 비아 구조를 포함하는 3차원 반도체 소자 및 그 형성 방법
KR102867762B1 (ko) * 2019-10-31 2025-10-13 삼성전자주식회사 반도체 소자
KR102744273B1 (ko) 2020-01-03 2024-12-19 에스케이하이닉스 주식회사 반도체 장치 및 반도체 장치의 제조 방법
CN111223872B (zh) * 2020-01-17 2023-04-07 长江存储科技有限责任公司 一种3d nand存储器及其制造方法
KR102815720B1 (ko) * 2020-01-23 2025-06-02 삼성전자주식회사 폴리 실리콘과 메탈을 포함하는 워드 라인을 갖는 3차원 메모리 소자 및 이의 제조 방법
TWI743836B (zh) * 2020-04-30 2021-10-21 大陸商長江存儲科技有限責任公司 立體記憶體元件及其製作方法
KR102752667B1 (ko) 2020-05-07 2025-01-10 에스케이하이닉스 주식회사 반도체 장치 및 반도체 장치의 제조 방법
KR20210155266A (ko) * 2020-06-15 2021-12-22 에스케이하이닉스 주식회사 반도체 장치 및 반도체 장치의 제조 방법
CN111785730B (zh) * 2020-06-18 2021-06-08 长江存储科技有限责任公司 三维存储器及制备方法、电子设备
US12513973B2 (en) * 2022-02-16 2025-12-30 Samsung Electronics Co., Ltd. Wafer structure and semiconductor device

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US20150145015A1 (en) 2013-11-26 2015-05-28 Yoocheol Shin Three-dimensional semiconductor memory device
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US20170084624A1 (en) 2015-09-18 2017-03-23 Changhyun LEE Three-dimensional semiconductor device with vertical and horizontal channels in stack structure having electrodes vertically stacked on the substrate

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US20150145015A1 (en) 2013-11-26 2015-05-28 Yoocheol Shin Three-dimensional semiconductor memory device
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Publication number Publication date
KR102332346B1 (ko) 2021-12-01
CN108695339B (zh) 2023-09-05
US20180294274A1 (en) 2018-10-11
KR20180114566A (ko) 2018-10-19
JP2018182320A (ja) 2018-11-15
CN108695339A (zh) 2018-10-23
US10396088B2 (en) 2019-08-27

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