JP7207859B2 - ３次元半導体メモリ装置及びその製造方法 - Google Patents

３次元半導体メモリ装置及びその製造方法 Download PDF

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Publication number
JP7207859B2
JP7207859B2 JP2018074160A JP2018074160A JP7207859B2 JP 7207859 B2 JP7207859 B2 JP 7207859B2 JP 2018074160 A JP2018074160 A JP 2018074160A JP 2018074160 A JP2018074160 A JP 2018074160A JP 7207859 B2 JP7207859 B2 JP 7207859B2
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vertical
pattern
semiconductor
semiconductor pattern
memory device
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JP2018182320A (ja
JP2018182320A5 (enExample
Inventor
昭 賢 李
善 一 沈
載 悳 李
在 薫 張
智 勳 韓
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/693—Vertical IGFETs having charge trapping gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H10D84/0133—Manufacturing common source or drain regions between multiple IGFETs

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Electroluminescent Light Sources (AREA)
  • Thin Film Transistor (AREA)
JP2018074160A 2017-04-10 2018-04-06 ３次元半導体メモリ装置及びその製造方法 Active JP7207859B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2017-0046229 2017-04-10
KR1020170046229A KR102332346B1 (ko) 2017-04-10 2017-04-10 3차원 반도체 메모리 장치 및 그의 제조 방법

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JP2018182320A JP2018182320A (ja) 2018-11-15
JP2018182320A5 JP2018182320A5 (enExample) 2021-04-22
JP7207859B2 true JP7207859B2 (ja) 2023-01-18

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US (1) US10396088B2 (enExample)
JP (1) JP7207859B2 (enExample)
KR (1) KR102332346B1 (enExample)
CN (1) CN108695339B (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020017572A (ja) * 2018-07-23 2020-01-30 キオクシア株式会社 半導体メモリ及び半導体メモリの製造方法
CN110062958B (zh) 2019-03-04 2020-05-26 长江存储科技有限责任公司 用于形成三维存储器件的方法
WO2020177048A1 (en) 2019-03-04 2020-09-10 Yangtze Memory Technologies Co., Ltd. Three-dimensional memory devices
KR102778239B1 (ko) * 2019-04-25 2025-03-10 삼성전자주식회사 수직형 반도체 소자
EP4521880A3 (en) 2019-06-27 2025-05-14 Yangtze Memory Technologies Co., Ltd. Novel 3d nand memory device and method of forming the same
KR102728797B1 (ko) * 2019-07-31 2024-11-11 삼성전자주식회사 반도체 장치 및 이의 동작 방법
KR102801211B1 (ko) * 2019-10-29 2025-04-29 삼성전자주식회사 돌출한 비아 라이너 층을 갖는 관통 비아 구조를 포함하는 3차원 반도체 소자 및 그 형성 방법
CN111223872B (zh) * 2020-01-17 2023-04-07 长江存储科技有限责任公司 一种3d nand存储器及其制造方法
CN111771281B (zh) * 2020-01-17 2021-07-20 长江存储科技有限责任公司 三维存储器件及其制作方法
KR102815720B1 (ko) * 2020-01-23 2025-06-02 삼성전자주식회사 폴리 실리콘과 메탈을 포함하는 워드 라인을 갖는 3차원 메모리 소자 및 이의 제조 방법
TWI743836B (zh) * 2020-04-30 2021-10-21 大陸商長江存儲科技有限責任公司 立體記憶體元件及其製作方法
KR102752667B1 (ko) 2020-05-07 2025-01-10 에스케이하이닉스 주식회사 반도체 장치 및 반도체 장치의 제조 방법
KR20210155266A (ko) * 2020-06-15 2021-12-22 에스케이하이닉스 주식회사 반도체 장치 및 반도체 장치의 제조 방법
CN111785730B (zh) * 2020-06-18 2021-06-08 长江存储科技有限责任公司 三维存储器及制备方法、电子设备
KR20230123355A (ko) * 2022-02-16 2023-08-23 삼성전자주식회사 웨이퍼 구조체 및 반도체 소자

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120098139A1 (en) 2010-10-21 2012-04-26 Samsung Electronics Co., Ltd. Vertical Memory Devices And Methods Of Manufacturing The Same
US20150145015A1 (en) 2013-11-26 2015-05-28 Yoocheol Shin Three-dimensional semiconductor memory device
US20160343730A1 (en) 2015-05-19 2016-11-24 Yong-Hoon Son Vertical Memory Devices
US20170084624A1 (en) 2015-09-18 2017-03-23 Changhyun LEE Three-dimensional semiconductor device with vertical and horizontal channels in stack structure having electrodes vertically stacked on the substrate

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010080685A (ja) 2008-09-26 2010-04-08 Toshiba Corp 不揮発性記憶装置及びその製造方法
JP5279560B2 (ja) 2009-03-11 2013-09-04 株式会社東芝 不揮発性半導体記憶装置
US8349681B2 (en) * 2010-06-30 2013-01-08 Sandisk Technologies Inc. Ultrahigh density monolithic, three dimensional vertical NAND memory device
DE102011084603A1 (de) * 2010-10-25 2012-05-16 Samsung Electronics Co., Ltd. Dreidimensionales Halbleiterbauelement
KR20130066950A (ko) * 2011-12-13 2013-06-21 에스케이하이닉스 주식회사 3차원 불휘발성 메모리 소자와, 이를 포함하는 메모리 시스템과, 그 제조방법
US8847302B2 (en) * 2012-04-10 2014-09-30 Sandisk Technologies Inc. Vertical NAND device with low capacitance and silicided word lines
US9076879B2 (en) * 2012-09-11 2015-07-07 Samsung Electronics Co., Ltd. Three-dimensional semiconductor memory device and method for fabricating the same
KR20140117212A (ko) * 2013-03-26 2014-10-07 에스케이하이닉스 주식회사 반도체 장치
JP2015028990A (ja) 2013-07-30 2015-02-12 株式会社東芝 不揮発性記憶装置
JP2015149413A (ja) 2014-02-06 2015-08-20 株式会社東芝 半導体記憶装置及びその製造方法
KR102307487B1 (ko) * 2014-06-23 2021-10-05 삼성전자주식회사 3차원 반도체 메모리 장치 및 그 제조 방법
KR20160006866A (ko) 2014-07-09 2016-01-20 삼성전자주식회사 반도체 장치 및 그 제조방법
US9773803B2 (en) 2014-09-08 2017-09-26 Toshiba Memory Corporation Non-volatile memory device and method of manufacturing same
US9362298B2 (en) 2014-09-11 2016-06-07 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and manufacturing method thereof
KR102275543B1 (ko) * 2014-10-27 2021-07-13 삼성전자주식회사 3차원 반도체 메모리 장치
US20160260736A1 (en) 2015-03-03 2016-09-08 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20160268282A1 (en) 2015-03-13 2016-09-15 Kabushiki Kaisha Toshiba Semiconductor memory device and method for manufacturing same
US9627399B2 (en) * 2015-07-24 2017-04-18 Sandisk Technologies Llc Three-dimensional memory device with metal and silicide control gates
KR102437779B1 (ko) * 2015-08-11 2022-08-30 삼성전자주식회사 3차원 반도체 메모리 장치
KR102437416B1 (ko) * 2015-08-28 2022-08-30 삼성전자주식회사 3차원 반도체 메모리 장치
KR20170027571A (ko) * 2015-09-02 2017-03-10 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
KR102440221B1 (ko) * 2015-09-09 2022-09-05 삼성전자주식회사 반도체 소자 및 이의 제조 방법
KR20170036878A (ko) * 2015-09-18 2017-04-03 삼성전자주식회사 3차원 반도체 메모리 장치
CN105355602B (zh) * 2015-10-19 2018-09-18 中国科学院微电子研究所 三维半导体器件及其制造方法
KR102565717B1 (ko) 2016-06-22 2023-08-14 삼성전자주식회사 메모리 장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120098139A1 (en) 2010-10-21 2012-04-26 Samsung Electronics Co., Ltd. Vertical Memory Devices And Methods Of Manufacturing The Same
US20150145015A1 (en) 2013-11-26 2015-05-28 Yoocheol Shin Three-dimensional semiconductor memory device
US20160343730A1 (en) 2015-05-19 2016-11-24 Yong-Hoon Son Vertical Memory Devices
US20170084624A1 (en) 2015-09-18 2017-03-23 Changhyun LEE Three-dimensional semiconductor device with vertical and horizontal channels in stack structure having electrodes vertically stacked on the substrate

Also Published As

Publication number Publication date
KR102332346B1 (ko) 2021-12-01
CN108695339A (zh) 2018-10-23
US10396088B2 (en) 2019-08-27
CN108695339B (zh) 2023-09-05
JP2018182320A (ja) 2018-11-15
KR20180114566A (ko) 2018-10-19
US20180294274A1 (en) 2018-10-11

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