JP7161043B2 - SiC半導体装置 - Google Patents
SiC半導体装置 Download PDFInfo
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- JP7161043B2 JP7161043B2 JP2021520842A JP2021520842A JP7161043B2 JP 7161043 B2 JP7161043 B2 JP 7161043B2 JP 2021520842 A JP2021520842 A JP 2021520842A JP 2021520842 A JP2021520842 A JP 2021520842A JP 7161043 B2 JP7161043 B2 JP 7161043B2
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- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
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- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
Description
アクティブ領域12に形成されたMISFETは、その構造上、npn型の寄生トランジスタを含む。外側領域13で生じたアバランシェ電流がアクティブ領域12に流れ込むと、寄生トランジスタがオン状態となる。この場合、ラッチアップによってMISFETの制御が不安定になる。そこで、SiC半導体装置1では、ソース主面電極81の構造を利用してアバランシェ電流吸収構造を形成している。
2 SiC半導体層
3 第1主面
21 ゲートトレンチ
22 ゲート絶縁層
23 ゲート電極
31 ソーストレンチ
32 ソース絶縁層
33 ソース電極
34 第1トレンチ部
35 第2トレンチ部
36 側壁窓部
39 側壁コンタクト部
41 ボディ領域
42 ソース領域
43 コンタクト領域
44 ディープウェル領域
67 ソース孔
69 リセス
85 ソース接続電極
91 絶縁層
131 SiC半導体装置
132 底壁窓部
134 底壁コンタクト部
151 SiC半導体装置
D1 ゲートトレンチの第1深さ
D2 ソーストレンチの第2深さ
W1 第1トレンチ部の第1幅
W2 第2トレンチ部の第2幅
Claims (23)
- 主面を有する第1導電型のSiC半導体層と、
前記主面に形成され、側壁および底壁を有するソーストレンチと、
前記ソーストレンチに埋設され、前記ソーストレンチの前記側壁において前記ソーストレンチの開口側の領域に接する側壁コンタクト部を有するソース電極と、
前記主面の表層部において前記ソーストレンチに沿う領域に形成された第2導電型のボディ領域と、
前記ボディ領域の表層部において前記ソース電極の前記側壁コンタクト部に電気的に接続された第1導電型のソース領域と、
前記ボディ領域の表層部において前記ソース電極の前記側壁コンタクト部に電気的に接続されるように前記ソース領域および前記ソース電極の前記側壁コンタクト部の間に介在され、前記ボディ領域の第2導電型不純物濃度を超える第2導電型不純物濃度を有する第2導電型のコンタクト領域と、を含む、SiC半導体装置。 - 前記ボディ領域は、前記ソース電極の前記側壁コンタクト部に電気的に接続されている、請求項1に記載のSiC半導体装置。
- 前記主面の上において前記ソース領域を被覆する絶縁層をさらに含む、請求項1または2に記載のSiC半導体装置。
- 前記絶縁層は、前記主面の上において前記ソース電極の前記側壁コンタクト部を被覆している、請求項3に記載のSiC半導体装置。
- 前記絶縁層は、断面視において前記ソース領域の全域を被覆している、請求項3または4に記載のSiC半導体装置。
- 前記絶縁層は、平面視において前記ソース領域の全域を被覆している、請求項3~5のいずれか一項に記載のSiC半導体装置。
- 前記絶縁層に形成され、前記ソース電極を露出させるソース孔と、
前記ソース孔に埋設され、前記ソース電極に接続されたソース接続電極と、を含む、請求項3~6のいずれか一項に記載のSiC半導体装置。 - 前記ソース接続電極は、前記ソース電極とは異なる導電材料を含む、請求項7に記載のSiC半導体装置。
- 前記ソース孔は、前記ソース電極のみを露出させており、
前記ソース接続電極は、前記ソース孔内において前記ソース電極のみに接続されている、請求項7または8に記載のSiC半導体装置。 - 前記ソース電極は、前記ソーストレンチの前記底壁に向けて窪んだリセスを有する電極面を含み、
前記ソース孔は、前記ソース電極の前記リセスに連通している、請求項7~9のいずれか一項に記載のSiC半導体装置。 - 前記ソース電極は、金属材料以外の導電材料からなる、請求項1~10のいずれか一項に記載のSiC半導体装置。
- 前記ソース電極は、導電性ポリシリコンからなる、請求項1~11のいずれか一項に記載のSiC半導体装置。
- 前記ソース電極は、p型ポリシリコンからなる、請求項1~12のいずれか一項に記載のSiC半導体装置。
- 前記ソーストレンチは、第1幅で開口側に形成された第1トレンチ部、および、前記第1幅未満の第2幅で前記底壁側に形成された第2トレンチ部を含み、
前記ソース電極の前記側壁コンタクト部は、前記第1トレンチ部から露出している、請求項1~13のいずれか一項に記載のSiC半導体装置。 - 複数の前記コンタクト領域が、前記ソーストレンチに沿って間隔を空けて形成されている、請求項1~14のいずれか一項に記載のSiC半導体装置。
- 前記コンタクト領域は、前記ボディ領域および前記ソース電極の前記側壁コンタクト部の間に介在している、請求項1~15のいずれか一項に記載のSiC半導体装置。
- 前記コンタクト領域は、前記ソーストレンチの前記側壁および前記底壁を被覆している、請求項1~16のいずれか一項に記載のSiC半導体装置。
- 前記主面の表層部において前記ボディ領域の下方の領域で前記ソーストレンチに沿って形成され、前記コンタクト領域の第2導電型不純物濃度未満の第2導電型不純物濃度を有する第2導電型のディープウェル領域をさらに含む、請求項1~17のいずれか一項に記載のSiC半導体装置。
- 前記ディープウェル領域は、前記ソーストレンチの前記側壁および前記底壁を被覆している、請求項18に記載のSiC半導体装置。
- 前記主面に形成されたゲートトレンチと、
前記ゲートトレンチの内壁に形成されたゲート絶縁層と、
前記ゲート絶縁層を挟んで前記ゲートトレンチに埋設されたゲート電極と、をさらに含む、請求項1~19のいずれか一項に記載のSiC半導体装置。 - 前記ゲートトレンチは、第1深さを有しており、
前記ソーストレンチは、前記第1深さを超える第2深さを有している、請求項20に記載のSiC半導体装置。 - 前記ソーストレンチの開口側の領域において前記ソーストレンチの前記側壁を露出させる側壁窓部を有し、前記ソーストレンチの前記側壁および前記底壁を被覆するソース絶縁層をさらに含み、
前記ソース電極の前記側壁コンタクト部は、前記側壁窓部から露出する前記ソーストレンチの前記側壁に接している、請求項1~21のいずれか一項に記載のSiC半導体装置。 - 前記ソーストレンチの前記側壁において前記ソーストレンチの開口側の領域を露出させる側壁窓部、および、前記ソーストレンチの前記底壁を露出させる底壁窓部を有し、少なくとも前記ソーストレンチの前記側壁を被覆するソース絶縁層をさらに含み、
前記ソース電極は、前記ソース絶縁層を挟んで前記ソーストレンチに埋設され、前記側壁窓部から露出する前記ソーストレンチの前記側壁に接する前記側壁コンタクト部、および、前記底壁窓部から露出する前記ソーストレンチの前記底壁に接する底壁コンタクト部を有している、請求項1~21のいずれか一項に記載のSiC半導体装置。
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