JP7007745B2 - 保護キャップ層を用いるプラチナ含有薄膜のエッチング - Google Patents
保護キャップ層を用いるプラチナ含有薄膜のエッチング Download PDFInfo
- Publication number
- JP7007745B2 JP7007745B2 JP2019539226A JP2019539226A JP7007745B2 JP 7007745 B2 JP7007745 B2 JP 7007745B2 JP 2019539226 A JP2019539226 A JP 2019539226A JP 2019539226 A JP2019539226 A JP 2019539226A JP 7007745 B2 JP7007745 B2 JP 7007745B2
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- platinum
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- C—CHEMISTRY; METALLURGY
- C01—INORGANIC CHEMISTRY
- C01G—COMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLASSES C01D OR C01F
- C01G55/00—Compounds of ruthenium, rhodium, palladium, osmium, iridium, or platinum
- C01G55/004—Oxides; Hydroxides
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- C—CHEMISTRY; METALLURGY
- C01—INORGANIC CHEMISTRY
- C01G—COMPOUNDS CONTAINING METALS NOT COVERED BY SUBCLASSES C01D OR C01F
- C01G55/00—Compounds of ruthenium, rhodium, palladium, osmium, iridium, or platinum
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/40—Resistors
- H10D1/47—Resistors having no potential barriers
- H10D1/474—Resistors having no potential barriers comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides
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- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
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- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
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- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
- H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
- H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
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- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
- H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
- H10D64/0131—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
- H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
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- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
- H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
- H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
- H10P50/285—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means of materials not containing Si, e.g. PZT or Al2O3
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- H10P50/60—Wet etching
- H10P50/66—Wet etching of conductive or resistive materials
- H10P50/663—Wet etching of conductive or resistive materials by chemical means only
- H10P50/667—Wet etching of conductive or resistive materials by chemical means only by liquid etching only
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- H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
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- H10P70/00—Cleaning of wafers, substrates or parts of devices
- H10P70/20—Cleaning during device manufacture
- H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
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- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
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- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
- H10W20/0633—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material using subtractive patterning of the conductive members
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- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/43—Layouts of interconnections
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- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/44—Conductive materials thereof
- H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
- H10W20/4432—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
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- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
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- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0172—Manufacturing their gate conductors
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- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
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- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
- H10W72/01251—Changing the shapes of bumps
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- H10W72/01—Manufacture or treatment
- H10W72/019—Manufacture or treatment of bond pads
- H10W72/01931—Manufacture or treatment of bond pads using blanket deposition
- H10W72/01933—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
- H10W72/01935—Manufacture or treatment of bond pads using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
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- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07531—Techniques
- H10W72/07532—Compression bonding, e.g. thermocompression bonding
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- H10W72/251—Materials
- H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
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- H10W72/921—Structures or relative sizes of bond pads
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- H10W72/951—Materials of bond pads
- H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
Landscapes
- Chemical & Material Sciences (AREA)
- Organic Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- ing And Chemical Polishing (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021212952A JP7244030B2 (ja) | 2017-01-19 | 2021-12-27 | 保護キャップ層を用いるプラチナ含有薄膜のエッチング |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201762448138P | 2017-01-19 | 2017-01-19 | |
| US62/448,138 | 2017-01-19 | ||
| US15/714,169 | 2017-09-25 | ||
| US15/714,169 US10504733B2 (en) | 2017-01-19 | 2017-09-25 | Etching platinum-containing thin film using protective cap layer |
| PCT/US2018/014522 WO2018136795A2 (en) | 2017-01-19 | 2018-01-19 | Etching platinum-containing thin film using protective cap layer |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021212952A Division JP7244030B2 (ja) | 2017-01-19 | 2021-12-27 | 保護キャップ層を用いるプラチナ含有薄膜のエッチング |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2020507207A JP2020507207A (ja) | 2020-03-05 |
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| US10504733B2 (en) | 2017-01-19 | 2019-12-10 | Texas Instruments Incorporated | Etching platinum-containing thin film using protective cap layer |
| US11257745B2 (en) * | 2017-09-29 | 2022-02-22 | Intel Corporation | Electroless metal-defined thin pad first level interconnects for lithographically defined vias |
| US11011381B2 (en) | 2018-07-27 | 2021-05-18 | Texas Instruments Incorporated | Patterning platinum by alloying and etching platinum alloy |
| JP7036001B2 (ja) * | 2018-12-28 | 2022-03-15 | 三菱電機株式会社 | 半導体装置の製造方法 |
| US12607594B2 (en) | 2020-09-03 | 2026-04-21 | Texas Instruments Incorporated | ISFET biosensor |
| US11990369B2 (en) | 2021-08-20 | 2024-05-21 | Applied Materials, Inc. | Selective patterning with molecular layer deposition |
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| JP2008118088A (ja) | 2006-10-11 | 2008-05-22 | Fujitsu Ltd | 半導体装置の製造方法 |
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| US20100035401A1 (en) | 2008-08-11 | 2010-02-11 | Kuo-Chih Lai | Method for fabricating mos transistors |
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| EP3571709A2 (en) | 2019-11-27 |
| EP3571709B1 (en) | 2023-11-22 |
| WO2018136795A8 (en) | 2019-12-12 |
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| US10504733B2 (en) | 2019-12-10 |
| JP2022043249A (ja) | 2022-03-15 |
| EP3571709A4 (en) | 2020-02-12 |
| WO2018136795A2 (en) | 2018-07-26 |
| US20180204734A1 (en) | 2018-07-19 |
| US11929423B2 (en) | 2024-03-12 |
| US20210313179A1 (en) | 2021-10-07 |
| US20240222470A1 (en) | 2024-07-04 |
| CN117153816A (zh) | 2023-12-01 |
| JP7244030B2 (ja) | 2023-03-22 |
| WO2018136795A3 (en) | 2018-09-07 |
| CN110709966B (zh) | 2023-09-19 |
| JP2020507207A (ja) | 2020-03-05 |
| US20200083050A1 (en) | 2020-03-12 |
| US11069530B2 (en) | 2021-07-20 |
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