JP6876397B2 - 半導体メモリおよび半導体メモリの製造方法 - Google Patents
半導体メモリおよび半導体メモリの製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 239000010410 layer Substances 0.000 claims description 369
- 238000009792 diffusion process Methods 0.000 claims description 223
- 239000003990 capacitor Substances 0.000 claims description 102
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 76
- 229920005591 polysilicon Polymers 0.000 claims description 76
- 239000002344 surface layer Substances 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 25
- 239000012535 impurity Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims 1
- 230000006870 function Effects 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000012212 insulator Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 238000000926 separation method Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000012528 membrane Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000006386 memory function Effects 0.000 description 2
- 230000007334 memory performance Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000004043 responsiveness Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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Description
11 シリコン基板
20 第1のキャパシタ
21 nウェル
22a、22b n型拡散層
23a、23b、25 コンタクト
24 p型拡散層
26 第1の絶縁膜
27 第1の導電層
30 第2のキャパシタ
31 nウェル
32a、32b n型拡散層
33a、35 コンタクト
34 p型拡散層
36 第2の絶縁膜
37 第2の導電層
40 トランジスタ
42a ソース
43a、43b コンタクト
42b ドレイン
46 ゲート絶縁膜
47 ゲート電極
50 ポリシリコン膜
60 シリコン酸化膜
100A、100B メモリセルアレイ
Claims (10)
- 第1の導電型を有する第1の拡散層、前記第1の拡散層の表面に第1の絶縁膜を介して設けられた第1の導電層、前記第1の拡散層の表層部に設けられた前記第1の導電型を有する第2の拡散層、および前記第1の拡散層の表層部において前記第1の導電層に隣接し且つ前記第2の拡散層から離間して設けられた前記第1の導電型とは異なる第2の導電型の第3の拡散層を有する第1のキャパシタと、
前記第1の拡散層から離間して設けられた前記第1の導電型を有する第4の拡散層、前記第4の拡散層の表面に第2の絶縁膜を介して設けられ且つ前記第1の導電層に接続された第2の導電層、および前記第4の拡散層の表層部に設けられた前記第1の導電型を有する第5の拡散層、および前記第4の拡散層の表層部において前記第2の導電層に隣接し且つ前記第5の拡散層から離間して設けられた前記第2の導電型の第6の拡散層を有する第2のキャパシタと、
前記第1の導電層および前記第2の導電層に接続された第3の導電層をゲート電極として含み、前記ゲート電極を間に挟むように設けられたソースおよびドレインを構成する第1の導電型を有する第7の拡散層を含むトランジスタと、
を有し、
前記第1の導電層、前記第2の導電層および前記第3の導電層は、前記第1のキャパシタ、前記トランジスタ及び前記第2のキャパシタが並ぶ方向を長手方向とする単一のポリシリコン膜によって一体的に形成されており、
前記第2の拡散層、前記第7の拡散層及び前記第5の拡散層が、前記ポリシリコン膜の前記長手方向に沿ってこの順に並び、且つ前記ポリシリコン膜の前記長手方向に沿った辺に隣接して設けられており、前記第3の拡散層及び前記第6の拡散層が前記ポリシリコン膜の前記長手方向の端部において前記長手方向と交差する辺に隣接して設けられている
半導体メモリ。 - 前記第2の拡散層、前記第3の拡散層、前記第5の拡散層および前記第6の拡散層にそれぞれ接続された導電体からなるコンタクトを更に含む
請求項1に記載の半導体メモリ。 - 前記第2の拡散層は、前記第1の導電層に隣接して設けられ、
前記第5の拡散層は、前記第2の導電層に隣接して設けられている
請求項1または請求項2に記載の半導体メモリ。 - 前記第2の拡散層および前記第3の拡散層の不純物濃度は、前記第1の拡散層の不純物濃度よりも高く、
前記第5の拡散層および前記第6の拡散層の不純物濃度は、前記第4の拡散層の不純物濃度よりも高い
請求項1から請求項3のいずれか1項に記載の半導体メモリ。 - 前記ポリシリコン膜は、単一の導電型を有する
請求項1から請求項4のいずれか1項に記載の半導体メモリ。 - 前記第1の導電層の面積は、前記第2の導電層の面積よりも大である
請求項1から請求項5のいずれか1項に記載の半導体メモリ。 - 前記第1の導電層および前記第2の導電層は、それぞれ、複数の辺を有し、
前記第2の拡散層および前記第3の拡散層は、前記第1の導電層の互いに異なる辺に隣接して設けられ、
前記第5の拡散層および前記第6の拡散層は、前記第2の導電層の互いに異なる辺に隣接して設けられている
請求項1から請求項6のいずれか1項に記載の半導体メモリ。 - 第1の導電型を有する第1の拡散層、前記第1の拡散層の表面に第1の絶縁膜を介して設けられた第1の導電層、前記第1の拡散層の表層部に設けられた前記第1の導電型を有する第2の拡散層、および前記第1の拡散層の表層部において前記第1の導電層に隣接し且つ前記第2の拡散層から離間して設けられた前記第1の導電型とは異なる第2の導電型の第3の拡散層を有する第1のキャパシタを形成する工程と、
前記第1の拡散層から離間して設けられた前記第1の導電型を有する第4の拡散層、前記第4の拡散層の表面に第2の絶縁膜を介して設けられ且つ前記第1の導電層に接続された第2の導電層、および前記第4の拡散層の表層部に設けられた前記第1の導電型を有する第5の拡散層、および前記第4の拡散層の表層部において前記第2の導電層に隣接し且つ前記第5の拡散層から離間して設けられた前記第2の導電型の第6の拡散層を有する第2のキャパシタを形成する工程と、
前記第1の導電層および前記第2の導電層に接続された第3の導電層をゲート電極として含み、前記ゲート電極を間に挟むように設けられたソースおよびドレインを構成する第1の導電型を有する第7の拡散層を含むトランジスタを形成する工程と、
を有し、
前記第1の導電層、前記第2の導電層および前記第3の導電層は、前記第1のキャパシタ、前記トランジスタ及び前記第2のキャパシタが並ぶ方向を長手方向とする単一のポリシリコン膜によって一体的に形成されており、
前記第2の拡散層、前記第7の拡散層及び前記第5の拡散層が、前記ポリシリコン膜の前記長手方向に沿ってこの順に並び、且つ前記ポリシリコン膜の前記長手方向に沿った辺に隣接して設けられており、前記第3の拡散層及び前記第6の拡散層が前記ポリシリコン膜の前記長手方向の端部において前記長手方向と交差する辺に隣接して設けられている
半導体メモリの製造方法。 - 前記第1のキャパシタおよび前記第2のキャパシタを形成する工程は、
半導体基板の表層部に前記第1の拡散層および前記第4の拡散層を形成する工程と、
前記第1の拡散層および前記第4の拡散層の表面を含む前記半導体基板の表面に、前記第1の絶縁膜および前記第2の絶縁膜を構成するシリコン酸化膜を形成する工程と、
前記シリコン酸化膜の表面に前記第1の導電層、前記第2の導電層および前記第3の導電層を構成するポリシリコン膜を形成する工程と、
前記ポリシリコン膜をパターニングする工程と、
前記第1の拡散層および前記第4の拡散層の表面に、それぞれ、前記第1の導電型を形成する不純物を注入して前記第2の拡散層および前記第5の拡散層を形成する工程と、
前記第1の拡散層および前記第4の拡散層の表面に、それぞれ、前記第2の導電型を形成する不純物を注入して前記第3の拡散層および前記第6の拡散層を形成する工程と、
を含む請求項8に記載の製造方法。 - 前記第2の拡散層、前記第3の拡散層、前記第5の拡散層および前記第6の拡散層を形成する前に、前記ポリシリコン膜の全面に不純物を注入する工程を更に含む
請求項9に記載の製造方法。
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