JP6871286B2 - 疑似スタティックランダムアクセスメモリの制御回路及び制御方法 - Google Patents

疑似スタティックランダムアクセスメモリの制御回路及び制御方法 Download PDF

Info

Publication number
JP6871286B2
JP6871286B2 JP2019029733A JP2019029733A JP6871286B2 JP 6871286 B2 JP6871286 B2 JP 6871286B2 JP 2019029733 A JP2019029733 A JP 2019029733A JP 2019029733 A JP2019029733 A JP 2019029733A JP 6871286 B2 JP6871286 B2 JP 6871286B2
Authority
JP
Japan
Prior art keywords
asynchronous
clock
cas
cas clock
count value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2019029733A
Other languages
English (en)
Japanese (ja)
Other versions
JP2020135912A (ja
Inventor
池田　仁史
仁史 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Winbond Electronics Corp
Original Assignee
Winbond Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Winbond Electronics Corp filed Critical Winbond Electronics Corp
Priority to JP2019029733A priority Critical patent/JP6871286B2/ja
Priority to CN201910232024.2A priority patent/CN111599395B/zh
Priority to KR1020190037037A priority patent/KR102196677B1/ko
Publication of JP2020135912A publication Critical patent/JP2020135912A/ja
Application granted granted Critical
Publication of JP6871286B2 publication Critical patent/JP6871286B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406—Refreshing of dynamic cells
    • G11C2211/4066—Pseudo-SRAMs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System (AREA)
JP2019029733A 2019-02-21 2019-02-21 疑似スタティックランダムアクセスメモリの制御回路及び制御方法 Active JP6871286B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2019029733A JP6871286B2 (ja) 2019-02-21 2019-02-21 疑似スタティックランダムアクセスメモリの制御回路及び制御方法
CN201910232024.2A CN111599395B (zh) 2019-02-21 2019-03-26 用于伪静态随机存取存储器的控制电路以及控制方法
KR1020190037037A KR102196677B1 (ko) 2019-02-21 2019-03-29 의사 스태틱 랜덤 액세스 메모리의 제어 회로 및 제어 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2019029733A JP6871286B2 (ja) 2019-02-21 2019-02-21 疑似スタティックランダムアクセスメモリの制御回路及び制御方法

Publications (2)

Publication Number Publication Date
JP2020135912A JP2020135912A (ja) 2020-08-31
JP6871286B2 true JP6871286B2 (ja) 2021-05-12

Family

ID=72191965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019029733A Active JP6871286B2 (ja) 2019-02-21 2019-02-21 疑似スタティックランダムアクセスメモリの制御回路及び制御方法

Country Status (3)

Country Link
JP (1) JP6871286B2 (ko)
KR (1) KR102196677B1 (ko)
CN (1) CN111599395B (ko)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005222581A (ja) * 2004-02-03 2005-08-18 Renesas Technology Corp 半導体記憶装置
TWI259466B (en) * 2005-03-16 2006-08-01 Winbond Electronics Corp Circuitry and method for adjusting signal length
US8239658B2 (en) * 2006-02-21 2012-08-07 Cypress Semiconductor Corporation Internally derived address generation system and method for burst loading of a synchronous memory
JP5262246B2 (ja) * 2008-03-31 2013-08-14 富士通セミコンダクター株式会社 半導体記憶装置およびメモリシステム
US10776192B2 (en) * 2015-09-17 2020-09-15 Hewlett Packard Enterprise Development Lp Memory store error check
JP6476325B1 (ja) * 2018-02-01 2019-02-27 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． 擬似ｓｒａｍ及びその制御方法

Also Published As

Publication number Publication date
JP2020135912A (ja) 2020-08-31
CN111599395B (zh) 2022-07-19
CN111599395A (zh) 2020-08-28
KR102196677B1 (ko) 2020-12-31
KR20200102890A (ko) 2020-09-01

Similar Documents

Publication Publication Date Title
JP5228468B2 (ja) システム装置およびシステム装置の動作方法
JP5011485B2 (ja) 半導体メモリ装置
US7489172B2 (en) DLL driver control circuit
JP4284527B2 (ja) メモリインターフェイス制御回路
JP5642524B2 (ja) 半導体装置
JP5098391B2 (ja) 半導体メモリ、システムおよび半導体メモリの動作方法
US20070171763A1 (en) Circuit and method for controlling write recovery time in semiconductor memory device
JP4717373B2 (ja) 半導体メモリ
US7657800B2 (en) Semiconductor memory device and method of performing a memory operation
JP2009117020A (ja) 半導体メモリ装置
JP2002015570A (ja) 半導体メモリ
KR20070036560A (ko) 반도체 메모리 장치의 지연고정루프
JP6871286B2 (ja) 疑似スタティックランダムアクセスメモリの制御回路及び制御方法
US10957378B1 (en) Control circuit and control method thereof for pseudo static random access memory
TWI694442B (zh) 用於偽靜態隨機存取記憶體的控制電路以及控制方法
JP2006228342A (ja) 半導体記憶装置
JP6874097B1 (ja) 擬似ｓｒａｍに使用する制御回路及びその制御方法
US7952957B2 (en) Circuit for generating read and signal and circuit for generating internal clock using the same
KR102265513B1 (ko) 의사 sram에 사용하는 제어 회로 및 그 제어 방법
CN112992222B (zh) 应用于伪静态随机存取存储器的控制电路及其控制方法
TWI709964B (zh) 應用於偽靜態隨機存取記憶體的控制電路及其控制方法
JP6999791B1 (ja) 半導体記憶装置
JP2006012357A (ja) メモリ装置
KR20020057689A (ko) 프리챠지 제어 회로를 구비한 반도체 메모리 장치

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190221

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200414

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200706

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20210105

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210312

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20210406

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20210415

R150 Certificate of patent or registration of utility model

Ref document number: 6871286

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250