JP6871286B2 - Pseudo-static random access memory control circuit and control method - Google Patents

Description

The present invention relates to a control circuit and a control method of a memory device, and more particularly to a control circuit and a control method of a pseudo-static random access memory.

In recent years, the integration of semiconductor memory devices has progressed, and high speeds have been required, and static random access memory (Static Random Access Memory, SRAM) and dynamic random access memory are used as high-speed memories. Demand for pseudo-static random access memory (Pseudo Static Random Access Memory, pSRAM), which has the advantages of dynamic random access memory (Dynamic Random Access Memory, DRAM), continues to increase, especially in operations for mobile devices.

The pseudo-static random access memory is a memory device having a cell structure of the dynamic random access memory and peripheral circuits of the static random access memory. Pseudo-static random access memory has the advantages of large capacity and low cost, but existing pseudo-static random access memory can write data synchronously or asynchronously if the clock period of the write operation is relatively short. In order to avoid the occurrence of an error, in the write operation, the column address strobe (CAS, hereinafter abbreviated as CAS) clock corresponding to the case where the data write is asynchronous (that is, the asynchronous mode of the write operation) is set. A control path for providing is established, and a control path for providing another CAS clock corresponding to the case of synchronization (ie, synchronous mode of write operation) is established. In this way, the pseudo-static random access memory can execute the synchronous mode or the asynchronous mode of the write operation by different control paths.

However, in the above method, since the clock cycle is short, when the pseudo static random access memory is switched from the asynchronous mode to the synchronous mode, the CAS clock is generated by the first clock of the route change after the control route is changed by changing the route. It may not be in time, which causes an error in the write operation.

The present invention provides a control circuit and a control method for a pseudo-static random access memory capable of executing a synchronous mode and an asynchronous mode of a write operation by a plurality of control paths in a write operation.

The control circuit of the present invention is applied to a pseudo static random access memory. The control circuit includes a first counter, a second counter, a comparator, an asynchronous controller, and a clock generator. The first counter is used to count the number of latches of data written to the pseudo-static random access memory based on the external clock and generate the first count value. The second counter is used to count the number of times the data written to the pseudo-static random access memory is written based on the asynchronous CAS clock and generate the second count value. The initial period of the asynchronous CAS clock is shorter than the period of the external clock. The comparator is coupled to the first counter and the second counter. The comparator is used to compare the first count value and the second count value. When the first count value is equal to the second count value, the comparator provides a first logic level mode signal. The asynchronous controller is coupled to the comparator and the second counter. The asynchronous controller is used to receive the mode signal and the CAS clock in the write operation and to provide the asynchronous CAS clock based on the CAS clock in the asynchronous mode. When the asynchronous controller first receives the mode signal of the first logic level, the asynchronous controller shifts the write operation from the asynchronous mode to the synchronous mode and adjusts the period of the asynchronous CAS clock to the period of the external clock. The clock generator is coupled to the asynchronous controller. A clock generator is used to provide a CAS clock based on an asynchronous CAS clock.

The control method of the present invention is applied to a pseudo-static random access memory. The control method provides a step of counting the number of latches of data written to the pseudo-static random access memory based on an external clock to generate a first count value, and an asynchronous CAS clock based on the CAS clock in the asynchronous mode. And a step to generate a second count value by counting the number of times the data written to the pseudo-static random access memory is written based on the asynchronous CAS clock, and the initial cycle of the asynchronous CAS clock is smaller than the cycle of the external clock. And, when the first count value and the second count value are compared and the first count value is equal to the second count value, the step of providing the mode signal of the first logic level and the mode signal of the first logic level first. Includes a step of shifting the write operation from the asynchronous mode to the synchronous mode and adjusting the period of the asynchronous CAS clock to the period of the external clock, and a step of providing the CAS clock based on the asynchronous CAS clock.

Based on the above, the control circuit of the present invention counts the number of times data is latched based on an external clock to generate a first count value, and counts the number of times data is written based on an asynchronous CAS clock to perform a second count. Generate a value and compare the first count value with the second count value. The control circuit provides an asynchronous CAS clock based on the CAS clock in asynchronous mode to provide the CAS clock. When the first count value first equals the second count value, the control circuit shifts the write operation from asynchronous mode to synchronous mode and adjusts the asynchronous CAS clock cycle to the external clock cycle to provide the CAS clock. To do. As described above, the present invention can eliminate the need to execute the motivational mode and the asynchronous mode of the writing operation by a plurality of control paths in the writing operation.

It is a circuit schematic diagram of the pseudo static random access memory which concerns on 1st Embodiment of this invention. It is a timing diagram of the writing operation which concerns on 1st Example. It is a circuit schematic diagram of the asynchronous controller which concerns on 1st Embodiment. It is the circuit schematic of the clock generator which concerns on 1st Example. It is a flowchart of the control method which concerns on 1st Example. It is a circuit schematic diagram of the control circuit which concerns on 2nd Embodiment of this invention. It is a timing diagram of the writing operation which concerns on 2nd Example. It is the circuit schematic of the synchronization controller which concerns on 2nd Embodiment. It is the circuit schematic of the clock generator which concerns on 2nd Example. It is a flowchart of the control method which concerns on 2nd Example.

In order to make the above-mentioned features and advantages of the present invention easier to understand, examples will be given and the drawings will be described in detail below.

Referring to FIG. 1, FIG. 1 is a schematic circuit diagram of a pseudo-static random access memory according to the first embodiment of the present invention. In this embodiment, the pseudo-static random access memory 100 includes a memory array 110 and a control circuit 120. The controller 120 is used to provide a column address strobe (CAS, hereinafter abbreviated as CAS) clock CASP to control the write operation of the memory array 110. The control circuit 120 includes a first counter 121, a second counter 122, a comparator 123, an asynchronous controller 124, and a clock generator 125. For example, the pseudo-static random access memory 100 further includes peripheral circuits such as an input / output circuit and a data latch. The first counter 121 is used to count the number of latches of data written to the pseudo-static random access memory 100 based on the external clock, thereby generating the first count value N_DIN. The first counter 121 counts the number of data latches of the data latch based on the external clock CLK, whereby the first count value N_DIN can be generated. When the data latch latches the data, the first counter 121 increases the first count value N_DIN based on the input display signal EN_DIN, where the input display signal EN_DIN is a status to indicate that the data has been input. It is a signal. The second counter 122 is used to count the number of times the data written to the pseudo-static random access memory 100 is written based on the asynchronous CAS clock CASP_A, and to generate the second count value N_DWR. The second counter 122 counts the number of times data is written to the memory array 110 based on the asynchronous CAS clock CASP_A, thereby generating a second count value N_DWR. When data is written to the memory array 110, the second counter 122 increases the second count value N_DWR based on the write display signal EN_WR, where the write display signal EN_WR indicates that the write operation is to be performed. It is a signal. The initial cycle of the asynchronous CAS clock CASP_A is smaller than the cycle of the external clock CLK. That is, in the write operation, the speed at which data is written to the memory array 10 is faster than the data latch speed. Therefore, the rate of increase of the second count value N_DWR is faster than the rate of increase of the first count value N_DIN.

The comparator 123 is coupled to the first counter 121 and the second counter 122. The comparator 123 compares the first count value N_DIN with the second count value N_DWR and determines whether or not the first count value N_DIN is equal to the second count value N_DWR. When the comparator 123 determines that the first count value N_DIN is equal to the second count value N_DWR, the first logic level mode signal ASYNC is provided. On the other hand, when the comparator 123 determines that the first count value N_DIN and the second count value N_DWR are not equal, the second logic level mode signal ASYNC is provided.

The asynchronous controller 124 is coupled to the comparator 123 and the second counter 122. The asynchronous controller 124 is used to receive the first logic level mode signal ASYNC and the CAS clock CASP during the write operation and to provide the asynchronous CAS clock CASP_A based on the CAS clock CASP in the asynchronous mode. When the asynchronous controller 124 first receives the first logic level mode signal ASYNC, it shifts the write operation from the asynchronous mode to the synchronous mode, thereby adjusting the period of the asynchronous CAS clock CASP_A to the period of the external clock. The clock generator 125 is coupled to the asynchronous controller 124. The clock generator 125 is used to provide the CAS clock CASP based on the asynchronous CAS clock CASP_A.

Specifically, FIGS. 1 and 2 are referred to at the same time, and FIG. 2 is a timing chart of the writing operation according to the first embodiment. In this embodiment, the data DQ starts to be input at time t1. Further, the input display signal EN_DIN indicating that the data DQ has been input transitions from the logic level low to the logic level high. At time t2, the first data D00 begins to be latched, the first counter 121 starts counting the number of times the data DQ is latched based on the external clock CLK, and generates the first count value N_DIN of "0". At this time, since the second count value N_DWR has not been generated yet, the first count value N_DIN and the second count value N_DWR are different. Therefore, the comparator 123 begins to provide a second logic level (ie, logic level high) mode signal at time t2. Next, at time t3, the writing operation is started. The write display signal EN_WR indicating that the write operation is executed transitions from the logic level low to the logic level high. At time t3, when the asynchronous controller 124 shifts to the write operation, the provision of the asynchronous CAS clock CASP_A is started. Since the initial cycle of the asynchronous CAS clock CASP_A is smaller than the cycle of the external clock CLK, the control circuit 120 shifts to the asynchronous operation mode. The second counter 122 starts counting the number of writes to the data of the pseudo static random access memory 100 based on the asynchronous CAS clock CASP_A, and generates a second count value N_DWR of "0". Further, the clock generator 125 provides a CAS clock CASP based on the asynchronous CAS clock CASP_A. Next, the first counter 121 and the second counter 122 continue counting. The rate of increase of the second count value N_DWR is faster than the rate of increase of the first count value N_DIN. Therefore, at time t4, the second count value N_DWR is equal to the first count value N_DIN (N_DWR = N_DIN = 8). This means that at time t4, all previously latched data D00-D08 will be written. Comparator 123 provides a first logic level (ie, logic level low) mode signal ASYNC. It should be noted that this means that when the asynchronous controller 124 first receives the first logic level mode signal ASYNC in the write operation (write display signal EN_WR is logic level high), the write operation is taken from the asynchronous mode. It means to shift to the synchronous mode. The asynchronous controller 124 does not provide the asynchronous CAS clock CASP_A based on the first logic level mode signal ASYNC. After that, when the first count value N_DIN is equal to 9 and the second count value N_DWR is equal to 8, the mode signal ASYNC is transitioned from the first logic level to the second logic level. At this time, the asynchronous controller 124 provides the asynchronous CAS clock CASP_A. In this way, the period of the asynchronous CAS clock CASP_A is gradually adjusted to the period of the external clock CLK, thereby achieving the effect of synchronizing the asynchronous CAS clock CASP_A with the external clock CLK. After time t4, the latches and writes of the data D09 to D13 are synchronized until the pseudo-static random access memory is in the standby state.

It should be mentioned that the control circuit 120 provides an asynchronous CAS clock CASP_A based on the CAS clock CASP in asynchronous mode to provide the CAS clock CASP. First, when the first count value N_DIN becomes equal to the second count value N_DWR, the control circuit 120 shifts the write operation from the asynchronous mode to the synchronous mode, and adjusts the period of the asynchronous CAS clock CASP_A to the period of the external clock. Provides a CAS clock. As described above, the present invention can eliminate the need to execute the synchronous mode and the asynchronous mode of the write operation via a plurality of control paths in the write operation.

Next, the subsection of the implementation of the asynchronous controller will be described. 1 and 3 are referred to at the same time, and FIG. 3 is a schematic circuit diagram of an asynchronous controller circuit according to the first embodiment. In this embodiment, the asynchronous controller 124 includes a timing adjustment unit 1242 and an asynchronous determination unit 1244. The timing regulator 1242 is coupled to the clock generator 125. The timing regulator 1242 receives the CAS clock CASP and is used to adjust the logical level low time length of the asynchronous CAS clock CASP_A based on the CAS clock CASP. The asynchronous determiner 1244 is coupled to the timing regulator 1242 and the clock generator 125. The asynchronous determiner 1244 is used to provide the asynchronous CAS clock CASP_A when receiving the second logic level mode signal ASYNC and the write display signal EN_WR corresponding to the transition to the write operation.

In this embodiment, the timing regulator 1242 includes inverters N01, N02, delayer D1, and NAND gate NAND1. The input of the inverter N01 is coupled to the clock generator 125 to receive the CAS clock CASP. The input end of the delay device D1 is coupled to the output end / inverter N01. The first input end of the NAND gate NAND1 is coupled to the output end of the inverter N01, and the second input end of the NAND gate NAND1 is coupled to the output end of the delay device D1. The input end of the inverter N02 is coupled to the output end of the NAND gate NAND1, and the output end of the inverter N02 is coupled to the asynchronous determiner 1244. The output end of the inverter N02 is used to output the asynchronous CAS clock CASP_A. In this embodiment, the timing regulator 1242 can determine the time length of the logical level low of the asynchronous CAS clock CASP_A by setting the time delay of the delay device D1.

The asynchronous determination unit 1244 includes a NAND gate NAND2 and an inverter N03. The first input end of the NAND gate NAND2 is coupled to the inverter N02 of the timing regulator 1242. The second input end of the NAND gate NAND1 is used to receive the mode signal ASYNC. The third input end of the NAND gate NAND1 is used to receive the write display signal EN_WR. The input end of the inverter N03 is coupled to the output end of the NAND gate NAND2. The output end of inverter N03 is used to provide the asynchronous CAS clock CASP_A. The asynchronous determiner 1244 provides an asynchronous CAS clock CASP_A when it receives the logic level high write display signal EN_WR and the logic level high mode signal ASYNC.

Next, the implementation subsection of the clock generator will be described. With reference to FIGS. 1, 3 and 4 at the same time, FIG. 4 is a schematic circuit diagram of a clock generator according to the first embodiment. In this embodiment, the clock generator 125 includes inverters N04, N05, flip-flops 1252 and timing regulators 1254, 1256. The input of the inverter N04 is coupled to the asynchronous controller 124 and receives the asynchronous CAS clock CASP_A. The set input end / S of the flip-flop 1252 is coupled to the output end of the inverter N04. The input end of the timing regulator 1254 is coupled to the output end Q of the flip-flop 1252. The input end of the inverter N05 is coupled to the output end of the timing regulator 1254. The output end of the inverter N05 is used to provide the CAS clock CASP. The input end of the timing regulator 1256 is coupled to the output end of the timing regulator 1254. The output end of the timing regulator 1256 is coupled to the reset input end / R of the flip-flop 1252. The timing adjustment unit 1256 can adjust the reset timing of the flip-flop 1252 based on the CAS clock CASP. The flip-flop 1252 of the present embodiment can be, for example, a set-reset (SR) latch composed of a plurality of NANDs, but the present invention is not limited thereto.

Further, the timing adjustment unit 1254 includes a delay device D2, an inverter N06, and a NAND gate NAND2. The input end of the delay device D2 is coupled to the output end Q of the flip-flop 1252. The input end of the inverter N06 is coupled to the delay device D2 at the output end. The first input end of the NAND gate NAND2 is coupled to the output end Q of the flip-flop 1252. The second input end of the NAND gate NAND2 is coupled to the output end of the inverter N06. The output end of the NAND gate NAND2 is coupled to the input of the inverter N05.

In this embodiment, under the cooperative operation of the asynchronous controller 124 and the clock generator 125, the timing regulator 1254 sets the time of the logical level high (that is, the pulse width) of the asynchronous CAS clock CASP_A by setting the time delay of the delay device D2. The length can be determined. Further, in the asynchronous timing regulator 1242, the time delay setting of the delay device D1 also indirectly determines the time length of the logic level low of the CAS clock CASP.

The timing regulator 1256 includes a delayer D3, an inverter N07 and a NAND gate NAND3. The input end of the delayer D3 is coupled to the output end of the timing regulator 1254. The input end of the inverter N07 is coupled to the delay device D3 at the output end. The first input end of the NAND gate NAND3 is coupled to the output end of the timing regulator 1254. The second input end of the NAND gate NAND3 is coupled to the output end of the inverter N07. The output end of the NAND gate NAND3 is coupled to the reset input end / R of the flip-flop 1252. In this embodiment, the timing regulator 1256 can be considered as a time reset flip-flop 1252 at the falling edge of the CAS clock PASS.

The logical level low duration of the CAS clock CSP may be related to the duration of precharging the data bus (data bus) of the pseudo-static random access memory. Therefore, the appropriate precharge time length can be determined by the time delay setting of the delay device D1 inside the asynchronous controller 124. The logical level high time length of the CAS clock CASP may be related to the time length required for the data read / write operation from the memory cell. Therefore, the appropriate read / write time can be determined by the time delay setting of the delay device D2 inside the clock generator 125.

1 and 5 are referred to at the same time, and FIG. 5 is a flowchart of a control method according to the first embodiment. In this embodiment, the control circuit 120 counts the number of latches of the data written in the pseudo-static random access memory 100 based on the external clock CLK in step S510, and generates the first count value N_DIN. After generating the first count value N_DIN in step S520, the control circuit 120 provides the asynchronous CAS clock CASP_A based on the CAS clock CASSP in asynchronous mode. In step S530, the control circuit 120 counts the number of times the data written to the pseudo-static random access memory is written based on the asynchronous CAS clock CASP_A, and generates a second count value N_DWR. The control circuit 120 compares the first count value N_DIN with the second count value N_DWR in step S540. In step S540, it is determined whether or not the first count value N_DIN is equal to the second count value N_DWR. When the control circuit 120 determines that the first count value N_DIN is not equal to the second count value N_DWR, the control circuit 120 maintains the asynchronous mode and proceeds to step S550. In step S550, the control circuit 120 provides the CAS clock CASP based on the asynchronous CAS clock CASP_A. When the control circuit 120 determines in step S540 that the first count value N_DIN is equal to the second count value N_DWR, the process proceeds to step S560, the mode signal ASYNC of the first logic level is provided, and the process proceeds to step S570. .. In step S570, the control circuit 120 shifts from asynchronous mode to synchronous mode based on the first logic level mode signal ASYNC initially provided, adjusts the period of the asynchronous CAS clock CASP_A to the period of the external clock, and steps. Move to S550. The subsections of the steps S510 to S570 have been described in detail in the above embodiments and will not be described again here.

With reference to FIG. 6, FIG. 6 is a schematic circuit diagram of a control circuit according to a second embodiment of the present invention. In this embodiment, the control circuit 620 is used to provide a CAS clock CASP to control the write operation of a memory array (not shown) of a pseudo-static random access memory. The control circuit 620 includes a first counter 621, a second counter 622, a comparator 623, an asynchronous controller 624, a clock generator 625, a synchronous write indicator 626, and a synchronous controller 627. The subsections of the implementation of the coordinated operation between the first counter 621, the second counter 622, the comparator 623 and the asynchronous controller 624 are not described again here as they are well taught in the first embodiment. In this embodiment, the synchronous write indicator 626 determines whether the first initial time for the pseudo-static random access memory to execute the write operation is earlier than the second initial time for latching the data written to the pseudo-static random access memory. Is used to determine. When the synchronous write indicator 626 determines that the first initial time is earlier than the second initial time, it provides the synchronous write display signal SYNCWR. On the other hand, when the synchronous write indicator 626 determines that the first initial time is slower or equal to the second initial time, the synchronous write display signal SYNCWR is not provided. The synchronization controller 627 is coupled to the synchronization write indicator 626 and the clock generator 625, and the synchronization controller 627 is enabled based on the synchronization write display signal SYNCWR and used to provide the synchronization CAS clock CASP_S based on the external clock CLK. Be done. When the clock generator 625 receives the synchronous CAS clock CASP_S, it provides the CAS clock CASP based on the synchronous CAS clock CASP_S.

Specifically, FIGS. 6 and 7 are referred to at the same time. FIG. 7 is a timing diagram of the writing operation according to the second embodiment. In this embodiment, the first initial time is the time ti1 at which the write display signal EN_WR for indicating that the write operation is performed first transitions from the logical level low to the logical level high. The second initial time is the time ti2 at which the input display signal EN_DIN for indicating that the data DQ has been input first transitions from the logic level low to the logic level high. When the synchronous write controller 626 determines that the first initial time (time ti1) is earlier than the second initial time (time ti2), it provides the synchronous write display signal SYNCWR. In this embodiment, the synchronous write indicator 626 is further coupled to the first counter 621 and the second counter 622. When the time ti1 is earlier than the time ti2, the first counter 621 is disabled based on the synchronous write display signal SYNCWR to stop providing the first count value N_DIN, and the second counter 622 stops providing the synchronous write display signal SYNCWR. The second count value N_DWR is disabled based on the above to stop providing the second count value N_DWR, and therefore the comparator 623 does not provide the second logic level mode signal ASYNC. This makes it impossible for the async controller 624 to provide the async CAS clock CASP_A. Further, the synchronization controller 627 is enabled based on the synchronization write display signal SYNCWR to provide the synchronization CAS clock CASP_S, thereby generating the CAS clock CASP. The period of the synchronous CAS clock CASP_S is equal to the period of the external clock CLK.

On the other hand, when the synchronous write indicator 626 determines that the first initial time (time ti1) is earlier than the second initial time (time ti2), the synchronous write display signal SYNCWR is not provided. If the synchronous write display signal SYNCWR is not provided, the first counter 621 can provide the first count value N_DIN, the second counter 622 can provide the second count value N_DWR, and the synchronous controller 627 is invalid. Be made. The subsections of the implementation when the synchronous write display signal SYNCWR is not provided are not described again here because they are fully taught in the examples of FIGS. 1 to 5.

As mentioned here, in the control circuit 620 of the second embodiment, the time when the data DQ starts to be written based on the above-mentioned first initial time and the second initial time is the time when the data DQ starts to be latched. It can be determined whether or not it is faster than. If the time at which the data DQ begins to be written is earlier than the time at which the data DQ begins to be latched, the control circuit 620 provides the synchronous CAS clock CASP_S and provides the CAS clock CASP based on the synchronous CAS clock CASP_S. In this way, the timing at which the data DQ is latched is synchronized with the timing at which the data DQ is written, and the timing at which the data DQ is latched does not catch up with the timing at which the data DQ is written.

Next, the implementation subsection of the synchronization controller will be described. 6 and 8 are referred to at the same time, and FIG. 8 is a schematic circuit diagram of the synchronization controller according to the second embodiment. In this embodiment, the synchronization controller 627 includes a NAND gate NAND4 and an inverter N07. The first input end of the NAND gate NAND4 is used to receive the external clock CLK. The second input end of the NAND gate NAND4 is used to receive the input display signal EN_DIN. The second input end of the NAND gate NAND4 is used to receive the synchronous write display signal SYNCWR provided by the synchronous write indicator 626. The input end of the inverter N07 is coupled to the output end of the NAND gate NAND4. The output end of the inverter N07 is used to provide the synchronous CAS clock CASP_S to the clock generator 625.

Next, the subsection of the implementation of the clock generator will be described. 6 and 9 are referred to at the same time, and FIG. 9 is a schematic circuit diagram of a clock generator according to a second embodiment. In this embodiment, the clock generator 625 includes inverters N08, N09, flip-flops 6252 and timing regulators 6254, 6256, 6258. The input end of the inverter N08 is coupled to the asynchronous controller 624 to receive the asynchronous CAS clock CASP_A. The first set input end / S1 of the flip-flop 6252 is coupled to the output end of the inverter N08. The input end of the timing regulator 6254 is coupled to the output end Q of the flip-flop 6252. The timing regulator 6254 may be the same as the timing regulator 1254 of FIG. 4, or it may be a simple modification of the timing regulator 1254 of FIG. The input end of the inverter N09 is coupled to the output end of the timing regulator 6254. The output end of inverter N09 is used to provide the CAS clock CASP. The input end of the timing regulator 6256 is coupled to the output end of the timing regulator 6254. The output end of the timing regulator 6256 is coupled to the reset input end / R of the flip-flop 6252. The timing regulator 6256 may be the same as the timing regulator 1254 of FIG. 4, or it may be a simple modification of the timing regulator 1256 of FIG. The timing adjustment unit 6256 can adjust the reset timing of the flip-flop 6252 based on the CAS clock CASP. The input end of the timing regulator 6258 is coupled to the synchronization controller 627 to receive the synchronization CAS clock CASP_S. The output end of the timing regulator 6258 is coupled to the second set input end / S2 of the flip-flop 6252. The flip-flop 6252 of the present embodiment can be, for example, a set reset (SR) latch composed of a plurality of NAND gates, and the present invention is not limited thereto.

The timing regulator 6258 includes a delayer D4, an inverter N10 and a NAND gate NAND5. The input end of the delay device D4 is coupled to the synchronization controller 627 to receive the synchronization CAS clock CASP_S. The input end of the inverter N10 is coupled to the output end of the delay device D4. The first input end of the NAND gate NAND 5 is coupled to the synchronization controller 627 to receive the synchronization CAS clock CASP_S. The second input end of the NAND gate NAND2 is coupled to the output end of the inverter N10. The output end of the NAND gate NAND2 is coupled to the second set input end / S2 of the flip-flop 6252.

6 and 10 are referred to at the same time, and FIG. 10 is a flowchart of a control method according to a second embodiment. In this embodiment, in step S1010, the control circuit receives a first initial time in which the pseudo-static random access memory executes a write operation and a second initial time in which the data written in the pseudo-static random access memory is latched. .. The control circuit 620 determines in step S1020 whether or not the first initial time is earlier than the second initial time. When it is determined that the first initial time is earlier than the second initial time, the control circuit 620 outputs the synchronous write display signal SYNCWR and proceeds to step S1030. In step S1030, the control circuit 620 provides the synchronous CAS clock CASP_S based on the synchronous write display signal SYNCWR and based on the external clock. Next, in step S1040, a CAS clock CASP is provided based on the synchronous CAS clock CASP_S. The subsections of the implementation of steps S101 to S1040 have been described in detail in the above embodiments and will not be described again here. On the other hand, when the control circuit 620 determines in step S1020 that the first initial time is slower or equal to the second initial time, the synchronous write display signal SYNCWR is not provided, and the process proceeds to step S510 of FIG. After the control circuit 620 shifts to step S510, the control method of the control circuit 620 becomes the same as the control method of the control circuit 120 of FIG. 1 (steps S510 to S570).

Integrating the above, the control circuit and control method of the present invention counts the number of times data is latched based on an external clock to generate a first count value, and counts the number of times data is written based on an asynchronous CAS clock. A second count value is generated, and the first count value and the second count value are compared. The control circuit and control method provide an asynchronous CAS clock based on the CAS clock in asynchronous mode and provide a CAS clock. When the first count value is equal to the second count value generated the first time, the control circuit and the control method change the write operation from the asynchronous mode to the synchronous mode, and adjust the period of the asynchronous CAS clock to the period of the external clock. , Provides a CAS clock. As described above, in the writing operation, it is not necessary to execute the synchronous mode and the asynchronous mode of the writing operation via a plurality of control paths. In addition, the control circuit and control method of the present invention can further determine whether or not the time at which data is started to be written is earlier than the time at which data is started to be latched. If the time at which the data begins to be written is earlier than the time at which the data is latched, the control circuit and control method will provide a synchronous CAS clock and will provide a CAS clock based on the synchronous CAS clock. In this way, the timing at which the data is latched and the timing at which the data is written are synchronized, and the timing at which the data is latched does not catch up with the timing at which the data is written.

The present invention discloses examples as described above, but it is not intended to limit the present invention, and those skilled in the art will make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is based on what is defined by the scope of claims described later.

The present invention relates to a pseudo-static random access memory and a control method. The control circuit and control method can support the write operation in the asynchronous mode and the write operation in the synchronous mode.

100 Pseudo-Static Random Access Memory 110 Memory Array,
120, 620 Control circuit 121, 621 1st counter 122, 622 2nd counter 123, 623 Comparer 124, 624 Asynchronous controller 1242, 1254, 1256, 6254, 6256, 6258 Timing adjuster 1244 Asynchronous judge 125, 625 Clock generator 1252 , 6252 Flip-flop 626 Synchronous write indicator 627 Synchronous controller ASYNC mode signal CASP CAS clock CASP_A Asynchronous CAS clock CASP_S Synchronous CAS clock CLK External clock D1, D2, D3, D4 Delayer DQ, D00 to D13 Data EN_DIN Input display signal EN_WR Write display Signals N01, N02, N03, N04, N05, N06, N07, N08, N09, N10 Inverter NAND1, NAND2, NAND3, NAND4, NAND5 NAND gate N_DIN 1st count value N_DWR 2nd count value Q Output end
/ R reset input end
/ S set input end
/ S1 1st set input end
/ S2 2nd set input terminal S510-S570 Step S101-1040 Step SYNCWR Synchronous write display signal t1, t2, t3, t4, ti1, ti2 time

Claims (14)

A control circuit applied to a pseudo-static random access memory, wherein the control circuit is
A first counter used to count the number of latches of data written to a pseudo-static random access memory based on an external clock and generate a first count value, and
It is used to count the number of writes of data written to the pseudo-static random access memory based on the asynchronous CAS clock to generate a second count value, and the initial cycle of the asynchronous CAS clock is from the cycle of the external clock. With a small second counter,
Combined with the first counter and the second counter, the first count value is compared with the second count value, and when the first count value is equal to the second count value, the mode of the first logic level. When a signal is provided and the first count value is not equal to the second count value, the mode signal of the second logic level is provided, and the second logic level is a comparator different from the first logic level.
Coupled with the comparator and the second counter, it is used to receive the mode signal and the CAS clock in the write operation and to provide the asynchronous CAS clock based on the CAS clock in the asynchronous mode, first the first logic. when receiving the mode signal of level, the write operation is shifted from the asynchronous mode to the synchronous mode, when the first logic level transitions to the second logic level, to provide the non-synchronous CAS clock Then, the cycle of the asynchronous CAS clock is gradually adjusted to the cycle of the external clock, and when the mode signal of the second logic level is first received and when the write operation is started, the asynchronous CAS clock is started to be provided. Asynchronous controller and
A clock generator coupled to the asynchronous controller and used to provide the CAS clock based on the asynchronous CAS clock.
Control circuit including. The asynchronous controller
A first timing regulator used to receive the CAS clock from the clock generator and adjust the logical level low time length of the asynchronous CAS clock based on the CAS clock.
When the output of the first timing regulator is received and the mode signal of the second logic level and the write enable signal corresponding to the transition to the write operation are received from the outside, the asynchronous CAS clock is changed to the clock. Asynchronous determiner used to provide to the generator and
The control circuit according to claim 1. The first timing adjuster
A first inverter whose input end is coupled to the clock generator to receive the CAS clock,
A delay device whose input end is coupled to the output end of the first inverter,
A NAND gate in which the first input end is coupled to the output end of the first inverter and the second input end is coupled to the output end of the delayer.
A second inverter whose input end is coupled to the output end of the NAND gate and whose output end is coupled to the asynchronous determination device.
Including
The control circuit according to claim 2, wherein the time length of the logical level low of the asynchronous CAS clock is determined by the time delay setting of the delay device. The clock generator
A first inverter whose input end is coupled to the asynchronous controller and receives the asynchronous CAS clock,
A flip-flop whose set input end is coupled to the output end of the first inverter,
Having a delayer, the input end is coupled to the output end of the flip-flop, and the time length of the logical level high of the CAS clock is adjusted by the time delay setting of the delayer based on the asynchronous CAS clock. The first timing adjuster, which is used for the output end and outputs the preparation result,
A second inverter in which the input end is coupled to the output end of the first timing regulator and the output end is used to provide a CAS clock.
The input end is coupled to the output end of the first timing regulator, the output end is coupled to the reset input end of the flip-flop, and used to adjust the reset timing of the flip-flop based on the asynchronous CAS clock. 2nd timing adjuster and
The control circuit according to claim 1. In addition
It is determined whether or not the first initial time for the pseudo-static random access memory to execute the write operation is earlier than the second initial time for latching the data written in the pseudo-static random access memory.
A synchronous write indicator used to provide a synchronous write display signal when it is determined that the first initial time is earlier than the second initial time.
A synchronous controller coupled to the synchronous write indicator and the clock generator and used to provide a synchronous CAS clock based on the external clock based on the synchronous write display signal.
The control circuit according to claim 1. The first counter is disabled based on the synchronous write display signal to stop providing the first count value, and the second counter is disabled based on the synchronous write display signal to stop providing the first count value. The control circuit according to claim 5, wherein the provision of the count value is stopped and the comparator is provided with the mode signal of the first logic level. The control circuit according to claim 5, wherein the clock generator is used to provide the CAS clock based on the synchronous CAS clock when the synchronous write display signal is provided. The clock generator
A first inverter whose input end is coupled to the asynchronous controller and receives the asynchronous CAS clock,
A flip-flop in which the input end of the first set is coupled to the output end of the first inverter,
Having a delayer, the input end is coupled to the output end of the flip-flop, and the time length of the logical level high of the CAS clock is adjusted by the time delay setting of the delayer based on the asynchronous CAS clock. The first timing adjuster, which is used for the output end and outputs the preparation result,
A second inverter in which the input end is coupled to the output end of the first timing regulator and the output end is used to provide the CAS clock.
The input end is coupled to the output end of the first timing regulator, the output end is coupled to the reset input end of the flip-flop, and used to adjust the reset timing of the flip-flop based on the asynchronous CAS clock. 2nd timing adjuster and
A third timing regulator whose input end is coupled to the sync controller to receive the synchronous CAS clock and whose output end is coupled to the second set input end of the flip-flop.
The control circuit according to claim 5. A control method applied to a pseudo-static random access memory and executed by a control circuit of the pseudo-static random access memory.
A step of counting the number of latches of data written to the pseudo-static random access memory based on an external clock to generate a first count value, and
Providing a non-synchronous CAS clock based on the CAS clock in asynchronous mode,
A second count value is generated by counting the number of times the data written to the pseudo-static random access memory is written based on the asynchronous CAS clock, and the initial cycle of the asynchronous CAS clock is smaller than the cycle of the external clock. With a certain step
The first count value is compared with the second count value, and when the first count value is equal to the second count value, a mode signal of the first logic level is provided, and the first count value is the first count value. The second logic level comprises providing the mode signal of the second logic level when it is not equal to the two count values, the second logic level being a step different from the first logic level.
First the write operation based on the first logic level of the mode signal provided shifted to synchronous mode from the asynchronous mode, when the first logic level transitions to the second logic level, the non-synchronous CAS By providing a clock, a step of gradually adjusting the period of the asynchronous CAS clock to the period of the external clock, and
Based on the asynchronous CAS clock, the step of providing the CAS clock and
A control method comprising first providing the asynchronous CAS clock when transitioning to the write operation when the mode signal of the second logic level is provided. The step in which the asynchronous mode provides the asynchronous CAS clock based on the CAS clock is
The control circuit receives the CAS clock via the timing regulator and adjusts the logical level low time length of the asynchronous CAS clock based on the CAS clock.
When the control circuit receives the mode signal of the second logic level and the write enable signal corresponding to the transition to the write operation via the asynchronous determiner, the asynchronous CAS clock is provided.
9. The control method according to claim 9. The step of providing the CAS clock based on the asynchronous CAS clock is
The control method according to claim 9, wherein the time length of the logical level high of the CAS clock is adjusted based on the asynchronous CAS clock. A step of determining whether or not the first initial time for the pseudo-static random access memory to execute the write operation is earlier than the second initial time for latching the data written in the pseudo-static random access memory.
When it is determined that the first initial time is earlier than the second initial time, the step of providing the synchronous write display signal and
A step of providing a synchronous CAS clock based on the external clock based on the synchronous write display signal, and
The control method according to claim 9, further comprising. The provision of the first count value is stopped based on the synchronous write display signal, the provision of the second count value is stopped based on the synchronous write display signal, and the mode signal of the first logic level is provided. The control method according to claim 12, further comprising a step. The control method according to claim 12, further comprising a step of providing the CAS clock based on the synchronous CAS clock when the synchronous write display signal is provided.

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