JP2006228342A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of improving the product yield by reducing write-in failure of data when a frequency of an external clock changes. <P>SOLUTION: The semiconductor storage device can perform writing operation with automatic pre-charge and comprises; a frequency detection circuit which compares a set frequency which is a predetermined clock frequency, with an external clock frequency, and outputs a detection signal showing a level relation between the set frequency and the external clock frequency; and a pre-charge signal generation circuit which changes the external clock frequency allotted to write recovery time for securing time for writing the data according to the level relation between the set frequency and the external clock frequency shown by the detection signal, and outputs a pre-charge start signal to start pre-charge operation after a lapse of the write recovery time. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device capable of a write operation with auto precharge.

  FIG. 4 is a timing chart showing the operation at the time of data writing of the conventional semiconductor memory device. FIG. 4 shows a burst operation in which a plurality of data is continuously written to a DDR (Double Data Rate) -SDRAM (Synchronous DRAM) in synchronization with an external clock CLK (CLKB is an inverted signal of CLK) supplied from the outside. The state of (burst length = 4) is shown.

  As shown in FIG. 4, when data (burst length = 4) is written, a write command (Write command) is input to the semiconductor memory device at time T0, and data D1 to D4 are data input / output terminals from time T1. Are sequentially input from the DQ terminal. Here, since a DDR-SDRAM is assumed as the semiconductor memory device, two data are input for each cycle of the external clock CLK. At this time, data D1 and D2 are written into the memory cell from time T2 (internal clock), and data D3 and D4 are written into the memory cell from time T3 (internal clock). Data D1 to D4 are written into the memory cells after the last data (here, data D4) is input and before the write recovery time tWR elapses.

  The write recovery time tWR is a specification value set according to the data write time to the memory cell, and is defined by the number of external clocks that can secure the required write time or the time.

  After the elapse of the write recovery time tWR, a precharge command for executing a well-known precharge operation that enables writing of the next data is input to the semiconductor memory device. The precharge command can be input after the writing operation of the data D1 to D4 to the memory cell is completed. For example, when the specification value of the write recovery time tWR is 15 nS, the cycle (tCK) of the external clock CLK is 7.5 nS. Then, it may be input after time T5 (tWR = 15 nS). If the period of the external clock CLK is 6 nS, it may be input after time T6 (tWR = 18 nS). If the period of the external clock CLK is 5 nS, time T6 is input. What is necessary is just to input after (tWR = 15nS).

  When the precharge command is input, after the Row precharge time tRP elapses, the precharge operation ends, and the next access (input of the Active command) to the same memory bank becomes possible.

  The Row precharge time tRP is a specification value set according to the precharge time to the memory cell, and is defined by the number of external clocks that can secure the necessary precharge time or the time.

  By the way, in a semiconductor memory device such as a DDR-SDRAM, an auto precharge operation in which a burst write operation of data or a burst read operation and a precharge operation are continuously executed by one command input is possible.

  For example, when a write command with auto precharge (Write-with-AP) is input, the semiconductor memory device first performs a data write operation in the same procedure as the timing chart shown in FIG. A precharge operation is executed by a precharge start signal issued internally.

  The conventional semiconductor memory device includes the precharge signal generation circuit shown in FIG. 5. When writing with auto-precharge, the precharge operation is automatically performed by outputting a precharge start signal from the precharge signal generation circuit after writing is completed. Has started.

  As shown in FIG. 5, the precharge signal generation circuit includes a first DF flip-flop (DF / F) 103 and a second DF / F 105 constituting the shift register, and a first D- An inverter 101 and a NAND circuit 102 for controlling the operation of the F / F 103, an OR-NAND circuit 104 for controlling the operation of the second DF / F 105, and an inverter 106 for outputting a precharge start signal to the outside. ing.

  An internal clock generated in the semiconductor memory device is input from a terminal A shown in FIG. 5, and a data write end signal generated by a control circuit (not shown) is input from a terminal C. The precharge start signal generated by the precharge signal generation circuit is output from the terminal E.

  The conventional precharge signal generation circuit delays the data write end signal inputted at time T3 shown in FIG. 4 by two cycles of the internal clock using a shift register composed of two DF / Fs. And output as a precharge start signal.

  Since the frequency of the internal clock is equal to that of the external clock CLK, the precharge signal generation circuit outputs a precharge start signal after two cycles of the external clock CLK have elapsed since the last data was input. That is, the number of external clocks CLK assigned to the write recovery time tWR (hereinafter referred to as the number of clocks of the write recovery time tWR) is set to “2”, and the precharge operation is started from time T5 shown in FIG. It was.

  A test mode signal indicating that the semiconductor memory device is in a test state is input to terminal B shown in FIG. When the test mode signal is “High”, the precharge signal generation circuit operates normally, and when the test signal is “Low”, the precharge signal generation circuit sets the number of clocks of the write recovery time tWR to “1”. To do. This is because when the semiconductor memory device is tested, an external clock CLK (tCK> several hundreds nS) having a low frequency is used, so that a sufficient data writing time can be secured even for one cycle of the external clock CLK. It is also for reducing the test time.

  As described above, in the precharge signal generation circuit shown in FIG. 5, since the number of clocks of the write recovery time tWR is set to “2”, when the specification value of the write recovery time tWR is 15 nS, the external clock If the period of CLK is 7.5 nS or more, the specification value of the write recovery time tWR can be satisfied. Here, when the frequency of the external clock CLK varies and the period becomes 6 nS to 7.5 nS, the write recovery time tWR becomes 12 nS to 15 nS, and the specification value cannot be satisfied. However, in the conventional semiconductor memory device, since the specification value of the write recovery time tWR has a relatively large margin with respect to the actually required write time, the clock number of the write recovery time tWR is fixed to “2”. Even writing was possible.

Note that, for example, Patent Document 1 and Patent Document 2 propose a configuration for stably operating the precharge even when the frequency of the external clock fluctuates.
JP 2001-210077 A JP 2001-344975 A

  In recent semiconductor memory devices, DDR-SDRAM having a data write / read speed (data rate) of 400 Mbps (tCK = 5 nS) has been realized as a result of the further increase in speed. In such a semiconductor memory device, if the number of clocks of the write recovery time tWR is fixed at “2”, it becomes 10 nS. Therefore, the write recovery time tWR greatly deviates from the specification value, and there is a risk of data writing failure. .

  Therefore, if the number of clocks of the write recovery time tWR is fixed at “3”, a sufficient writing time can be secured, so that a writing failure can be prevented. However, since the semiconductor memory device has a restriction on the total data write time (number of clocks) defined as tDAL (min) (= (tWR min + tRP min) / tCK), the write recovery time tWR If the number of clocks is fixed at “3”, there is a problem that the number of clocks that can be allocated to the Row precharge time tRP is reduced.

  Table 1 shows the relationship between the minimum value (number of CLKs) of tWR / tRP / tDAL and the period tCK of the external clock CLK in, for example, a DDR-SDRAM.

  If the write recovery time tWR shown in Table 1 cannot be ensured, a write failure occurs. If the Row precharge time tRP cannot be ensured, a write failure occurs, leading to a decrease in product yield.

  Note that DDR333 (2.5-3-3) and DDR400 (3-4-4) shown in Table 1 indicate the specifications of the DDR-SDRAM. For example, “333” indicates that the data rate is 333 Mbps (tCK = 6 nS), and “400” indicates that the data rate is 400 Mbps (tCK = 5 nS). Further, (2.5-3-3) indicates that Cas Latency = 2.5, tRCD = 3, tRP = 3 (both are the number of clocks), and similarly (3-4-4) is Cas Latency = 3, tRCD = 4, tRP = 4 (both are the number of clocks).

  Normally, at the time of writing with auto precharge, the distribution ratio between the write recovery time tWR and the row precharge time tRP can be freely set as long as the value of tDAL (min) is satisfied.

  Table 2-1 shows the relationship between the minimum value of tWR / tRP / tDAL (number of CLKs) and tCK when tWR = 2 is fixed in the conventional DDR-SDRAM, and Table 2-2 shows the conventional DDR. This shows the relationship between the minimum value of tWR / tRP / tDAL (the number of CLKs) and tCK when the SDRAM is fixed at tWR = 3.

  As shown in Table 2-1, when the conventional DDR-SDRAM is fixed at tWR = 2 (the number of clocks), the distribution ratio of tRP to tWR increases as the external clock frequency increases, and the write recovery time is increased. tWR cannot be secured.

  Further, as shown in Table 2-2, when the conventional DDR-SDRAM is fixed at tWR = 3 (number of clocks), the distribution ratio of tWR to tRP increases as the frequency of the external clock increases. The precharge time tRP cannot be secured.

  As a method for securing the time required for precharging, a method of starting precharging immediately after completion of data writing without synchronizing with the external clock CLK is conceivable. However, since the internal circuit operates on a relatively large scale at the time of precharging, there is a possibility that noise that is asynchronous with respect to the external clock may occur, causing malfunction of other circuits. Therefore, it is desirable to start the precharge operation in synchronization with the external clock.

  The present invention has been made to solve the above-described problems of the prior art, and a semiconductor memory device capable of reducing defective data writing when the frequency of an external clock is changed and improving the product yield. The purpose is to provide.

In order to achieve the above object, a semiconductor memory device of the present invention is a semiconductor memory device capable of a write operation with auto-precharge that continuously executes a data write operation and a precharge operation by one command input,
A frequency detection circuit that compares a set frequency, which is a predetermined clock frequency, with a frequency of an external clock, and outputs a detection signal indicating a level relationship between the set frequency and the frequency of the external clock;
The number of clocks of the external clock allocated to the write recovery time for securing the data write time is changed according to the level relationship between the set frequency indicated by the detection signal and the frequency of the external clock, and the write recovery A precharge signal generating circuit for outputting a precharge start signal for starting the precharge operation after a lapse of time;
It is the structure which has.

  In the semiconductor memory device configured as described above, since the number of clocks allocated to the write recovery time is changed according to the frequency of the external clock, the distribution ratio of the write recovery time and the row precharge time when writing with auto precharge is externally set. It can be set optimally according to the clock frequency.

  According to the present invention, by changing the number of clocks allocated to the write recovery time according to the frequency of the external clock, the distribution ratio of the write recovery time and the row precharge time at the time of writing with auto precharge is set to the frequency of the external clock. Since it can be set optimally correspondingly, data writing defects can be reduced and the yield of products can be improved.

  Next, the present invention will be described with reference to the drawings.

  In the semiconductor memory device of the present invention, a frequency detection circuit for detecting the frequency of the external clock CLK is added to the conventional precharge signal generation circuit shown in FIG. 4, and the precharge signal generated by the precharge signal generation circuit based on the output signal is added. In this configuration, the latency of the start signal is changed and the clock number of the write recovery time tWR is adjusted.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a semiconductor memory device of the present invention.

  As shown in FIG. 1, the semiconductor memory device of the first embodiment includes a precharge signal generation circuit 1 that generates a precharge start signal and a frequency detection circuit 2 that detects the frequency of an external clock CLK. It is.

  The precharge signal generation circuit 1 includes a first D-flip flop (DF / F) 14, a second DF / F 16 and a third DF / F 18 constituting a shift register, NAND circuit 12 and NOR circuit 13 for controlling the operation of DF / F 14, OR-NAND circuit 15 for controlling the operation of second DF / F 16, inverter 10 and NAND circuit 11, third circuit An OR-NAND circuit 17 that controls the operation of the DF / F 18 and an inverter 19 that outputs a precharge start signal to the outside are provided.

  An internal clock generated in the semiconductor memory device is input from a terminal A shown in FIG. 1, and a data write end signal generated by a control circuit (not shown) is input from a terminal C. The precharge start signal generated by the precharge signal generation circuit 1 is output from the terminal E. Further, the output signal (detection signal) of the frequency detection circuit 2 is input to the NAND circuit 12 and the inverter 10 of the precharge signal generation circuit 1.

  A test mode signal is input to the terminal B shown in FIG. 1 in the same manner as the conventional semiconductor memory device shown in FIG. 4, and the number of clocks of the write recovery time tWR is set to “1” when testing the semiconductor memory device. Is set.

  The frequency detection circuit 2 compares a predetermined clock frequency (hereinafter referred to as a set frequency) with the frequency of the external clock CLK, and outputs a detection signal indicating a level relationship between the set frequency and the frequency of the external clock CLK. For example, when the frequency of the external clock CLK is lower than the set frequency, the frequency detection circuit 2 outputs the “Low” level as the detection signal, and when the frequency of the external clock CLK is higher than the set frequency, the frequency detection circuit 2 sets the “High” level as the detection signal. Output. The frequency detection circuit 2 may have any configuration as long as it compares the set frequency described above with the frequency of the external clock CLK and outputs a detection signal indicating the level relationship between them. For example, the frequency detection circuit 2 may have the same configuration as the “lock mode determination circuit 320” described in FIG. 6 of Japanese Patent Application Laid-Open No. 2004-064143.

  The precharge signal generation circuit 1 receives the detection signal output from the frequency detection circuit 2, changes the number of clocks of the write recovery time tWR in accordance with the level relationship between the set frequency and the frequency of the external clock, and writes the write recovery time. A precharge start signal is output after elapse.

  Next, the operation of the semiconductor memory device of this embodiment will be described with reference to FIG.

  FIG. 2 is a timing chart showing the operation of the semiconductor memory device shown in FIG.

  2 is a burst operation (burst length = burst length = sequentially) written in synchronization with an external clock CLK (CLKB is an inverted signal of CLK) externally supplied to the DDR-SDRAM as in FIG. The state of 4) is shown.

As shown in FIG. 2, when writing data (burst length = 4), a write command with auto precharge is input to the semiconductor memory device at time T0, and data D1 to D4 are data input / output terminals from time T1. Sequentially input from a certain DQ terminal.
When writing data (burst length = 4), a write command (Write command) is input to the semiconductor memory device at time T0, and data D1 to D4 are sequentially input from the DQ terminal which is a data input / output terminal from time T1. Is done. At this time, the data D1 and D2 are written into the memory cell from time T2, and the data D3 and D4 are written into the memory cell from time T3.

  When the process of writing the data D1 to D4 into the memory cell is completed, a write end signal is output from a control circuit (not shown), and the first DF / F 14 and the second DF of the precharge signal generation circuit 1 are output. In / F16 and the third DF / F18, the write end signal is set at the timing of the internal clock at time T3, and the shift operation is started in synchronization with the internal clock from time T4.

  As described above, the frequency detection circuit 2 compares the frequency of the external clock CLK with the set frequency, and outputs a “High” level as a detection signal when the frequency of the external clock CLK is higher than the set frequency. When the frequency is lower than the set frequency, the “Low” level is output as the detection signal.

  Here, when the frequency of the external clock CLK is lower than the set frequency (tCK> set frequency), the detection signal D output from the frequency detection circuit 2 is at the “Low” level. The D-F / F 14 is set to the disabled state, and the second D-F / F 16 and the third D-F / F 18 are set to the enabled state.

  Therefore, the write end signal input from the terminal C is shifted by two internal clocks by the second DF / F 16 and the third DF / F 18 and precharged at the timing of the internal clock at time T5. A start signal E is output. At this time, the number of clocks of the write recovery time tWR is “2” (tWR = 2CLK). Here, this clock number “2” is defined as a standard number.

  On the other hand, when the frequency of the external clock CLK is higher than the set frequency (tCK <set frequency), the detection signal D output from the frequency detection circuit 2 is at “High” level. Each of the DF / F 14, the second DF / F 16, and the third DF / F 18 is set to an enable state.

  Therefore, the write end signal input from the terminal C is shifted by three internal clocks by the first DF / F 14, the second DF / F 16 and the third DF / F 18, and the time The precharge start signal E is output at the timing of the internal clock at T6. At this time, the number of clocks of the write recovery time tWR is “3” (tWR = 3CLK). That is, the number of clocks of the write recovery time tWR is the standard number + 1.

  In the semiconductor memory device of this embodiment, for example, when the period of the set frequency of the frequency detection circuit 2 is tCK = 7.5 nS, the performance shown in Table 3-1 can be realized. Note that the actual set frequency is preferably set to about tCK = 6 nS to 7 nS because the detection frequency varies due to manufacturing variations and use conditions.

  As described above, according to the semiconductor memory device of the present invention, since the number of clocks of the write recovery time tWR is changed according to the frequency of the external clock, the write recovery time tWR and the row precharge at the time of writing with auto precharge. The distribution ratio of time tRP can be optimally set corresponding to the frequency of the external clock. Therefore, data writing defects in the semiconductor memory device can be reduced and the yield of products can be improved.

(Second Embodiment)
Next, a semiconductor memory device according to a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 3 is a circuit diagram showing a configuration of the second embodiment of the semiconductor memory device of the present invention.

  As shown in FIG. 3, the semiconductor memory device of the second embodiment inserts an AND circuit 3 into the output of the frequency detection circuit shown in FIG. 1, and selects the output signal of the frequency detection circuit, for example, Cas Latency. It is a configuration that can be controlled by a signal. Since other configurations and operations are the same as those in the first embodiment, the description thereof is omitted.

  For example, when the SDRAM (DDR 400) is used with CL (Cas Latency) = 3, it is assumed that a high-frequency clock is used as the external clock CLK. In this embodiment, when CL (Cas Latency) = 3 is set (CL = 3 selection signal is “High” level), the operation of the precharge signal generation circuit is controlled by the detection signal output from the frequency detection circuit. Then, the number of clocks for the write recovery time tWR is changed in the same manner as in the first embodiment. On the other hand, when CL (Cas Latency) = 3 (CL = 3 selection signal is “L” level), the number of clocks of the write recovery time tWR is fixed at “2”.

  In the semiconductor memory device according to the second embodiment, when the period of the set frequency of the frequency detection circuit is tCK = 7.5 nS, the performance shown in Table 3-2 can be realized.

  As shown in Table 3-2, in the semiconductor memory device according to the second embodiment, the specification (about DDR333) in which the distribution ratio of the Row precharge time tRP is larger than the write recovery time tWR as compared with the first embodiment. ).

  According to the semiconductor memory device of the second embodiment, the same effect as that of the semiconductor memory device of the first embodiment can be obtained, and write recovery times tWR and Row can be obtained using various signals such as Cas Latency. The distribution ratio of the precharge time tRP can be controlled.

1 is a circuit diagram showing a configuration of a first embodiment of a semiconductor memory device of the present invention; 3 is a timing chart showing an operation of the semiconductor memory device shown in FIG. It is a circuit diagram which shows the structure of 2nd Embodiment of the semiconductor memory device of this invention. 6 is a timing chart showing an operation at the time of data writing of a conventional semiconductor memory device. It is a circuit diagram which shows the structure of the precharge signal generation circuit with which the conventional semiconductor memory device is provided.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Precharge signal generation circuit 2 Frequency detection circuit 3 AND circuit 10, 19 Inverter 11, 12 NAND circuit 13 NOR circuit 14 1st DF / F
15, 17 OR-NAND circuit 16 2nd DF / F
18 Third DF / F

Claims (4)

A semiconductor memory device capable of a write operation with auto-precharge that continuously executes a data write operation and a precharge operation by one command input,
A frequency detection circuit that compares a set frequency, which is a predetermined clock frequency, with a frequency of an external clock, and outputs a detection signal indicating a level relationship between the set frequency and the frequency of the external clock;
The number of clocks of the external clock allocated to the write recovery time for securing the data write time is changed according to the level relationship between the set frequency indicated by the detection signal and the frequency of the external clock, and the write recovery A precharge signal generating circuit for outputting a precharge start signal for starting the precharge operation after a lapse of time;
A semiconductor memory device. The precharge signal generation circuit includes:
When the detection signal indicates that the external clock is lower in frequency than the set frequency, the clock number of the external clock assigned to the write recovery time is a predetermined standard number,
When the detection signal indicates that the external clock is higher in frequency than the set frequency, the number of clocks of the external clock assigned to the write recovery time for securing the data write time is the standard number. 2. The semiconductor memory device according to claim 1, wherein +1 is set.   The semiconductor memory device according to claim 2, wherein the standard number is two. The precharge signal generation circuit includes:
4. The semiconductor memory device according to claim 1, wherein upon receiving a test mode signal indicating that the semiconductor memory device is in a test state, the number of clocks of the external clock assigned to the write recovery time is set to one.

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