TWI694442B - Control circuit and control method for pseudo static random access memory - Google Patents

Abstract

A control circuit and a control method for a pseudo static random access memory. The control circuit counts a number of latch times of the data based on an external clock to generate a first count value, counts a number of times of the data is written based on an asynchronous column address strobe clock to generate a second count value, and compares the first count value and the second count value. The control circuit provides a column address strobe clock according to the asynchronous column address strobe clock in an asynchronous mode. When the first occurrence of the first count value is equal to the second count value, the control circuit operates from the asynchronous mode of a write operation into a synchronous mode to adjust the period of the non-synchronous column address strobe clock to the period of the external clock.

Description

Control circuit and control method for pseudo-static random access memory

The present invention relates to a control circuit and a control method for a memory device, and particularly to a control circuit and a control method for a pseudo-static random access memory.

In recent years, as the level of integration of semiconductor memory devices has become higher and higher, there is a demand for higher speeds, static random access memory (SRAM) and dynamic random access memory (SRAM) Dynamic Random Access Memory (DRAM) is used as high-speed memory. The demand for pseudo static random access memory (PSRAM) with the advantages of dynamic random access memory (pSRAM) continues to increase, especially in mobile devices.

The pseudo-static random access memory is a memory element having a unit structure of dynamic random access memory and peripheral circuits of the static random access memory. Although pseudo Static random access memory has the advantages of large capacity and low cost. In the existing pseudo-static random access memory, when the clock cycle of the write operation is short, the writing of data may be synchronized or not. In order to avoid errors, in the write operation, the data is written in an asynchronous (ie, asynchronous mode of the write operation) to establish a control path to provide the corresponding row address strobe (column address strobe, CAS) clock, and in the case of synchronization (ie, the synchronization mode of the write operation), a control path is established to provide the corresponding row address strobe clock. In this way, the pseudo-static random access memory can perform the synchronous mode or the asynchronous mode of the write operation through different control paths.

However, in the above method, due to the short clock cycle, when the pseudo-static random access memory is switched from the asynchronous mode to the synchronous mode, it may be due to the change of the path. The changed first clock generates the row address strobe clock, which in turn causes an error in the write operation.

The invention provides a control circuit and a control method for a pseudo-static random access memory, which can perform a synchronous mode and an asynchronous mode of a write operation without using multiple control paths during a write operation.

The control circuit of the present invention is suitable for pseudo-static random access memory. The control circuit includes a first counter, a second counter, a comparator, an asynchronous controller, and a clock generator. The first counter is used to count the number of times the data written to the pseudo static random access memory is latched based on the external clock to generate a first count value. First The two counters are used to count the number of writes of the data written to the pseudo static random access memory based on the asynchronous row address strobe clock to generate a second count value. The initial period of the non-synchronized row address strobe clock is less than the period of the external clock. The comparator is coupled to the first counter and the second counter. The comparator is used to compare the first count value with the second count value. When the first count value is equal to the second count value, the comparator provides a mode signal of the first logic level. The asynchronous controller is coupled to the comparator. The asynchronous controller is used to receive the mode signal and the row address strobe clock in the write operation, and provide the asynchronous row address strobe clock according to the row address strobe clock in the asynchronous mode. When the asynchronous controller receives the mode signal of the first logic level for the first time, the asynchronous controller enters the write operation from the asynchronous mode into the synchronous mode to adjust the period of the strobe clock of the asynchronous row address It is the period of the external clock. The clock generator is coupled to the asynchronous controller. The clock generator is used to provide the row address strobe clock according to the asynchronous row address strobe clock.

The control method of the present invention is applicable to pseudo-static random access memory. The control method includes: counting the number of times the data written to the pseudo static random access memory is latched based on the external clock to generate a first count value; in the asynchronous mode, strobe clocking is provided according to the row address to provide asynchronous Row address strobe clock; counts the number of writes of data written to pseudo-static random access memory based on the asynchronous row address strobe clock to generate a second count value, where the non-synchronized row bit The initial period of the address strobe clock is less than the period of the external clock; compare the first count value with the second count value, where the mode signal of the first logic level is provided when the first count value is equal to the second count value; when the first When the mode signal of the first logic level is received once, the write operation is changed from asynchronous The mode enters the synchronous mode to adjust the period of the non-synchronized row address strobe clock to the period of the external clock; and provide the row address strobe clock according to the non-synchronized row address strobe clock.

Based on the above, the control circuit of the present invention counts the number of data latches based on an external clock to generate a first count value, and counts the number of data writes based on an asynchronous row address strobe clock to generate a second count Numerical value, and compare the first count value with the second count value. The control circuit provides the non-synchronized row address strobe clock according to the row address strobe clock in the asynchronous mode to provide the row address strobe clock. When the first count value is equal to the second count value for the first time, the control circuit changes the write operation from the asynchronous mode to the synchronous mode to adjust the period of the non-synchronized row address strobe clock to the period of the external clock. Provide row address strobe clock. In this way, the present invention can perform the synchronous mode and the asynchronous mode of the write operation without using multiple control paths during the write operation.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

100: pseudo-static random access memory

110: memory array

120, 620: control circuit

121, 621: First counter

122, 622: second counter

123, 623: comparator

124, 624: asynchronous controller

1242, 1254, 1256, 6254, 6256, 6258: timing adjuster

1244: Asynchronous judgment

125, 625: clock generator

1252, 6252: flip-flop

626: Synchronous write indicator

627: Synchronous controller

ASYNC: mode signal

CASP: row address strobe clock

CASP_A: Asynchronous row address strobe clock

CASP_S: Synchronous row address strobe clock

CLK: external clock

D1, D2, D3, D4: delay

DQ, D00~D13: data

EN_DIN: input indicator signal

EN_WR: write indicator signal

N01, N02, N03, N04, N05, N06, N07, N08, N09, N10: inverter

NAND1, NAND2, NAND3, NAND4, NAND5: Inverting gate

N_DIN: first count value

N_DWR: second count value

Q: output

/R: reset input

/S: Set input

/S1: the first setting input

/S2: second setting input

S510~S570: Steps

S1010~S1040: Steps

SYNCWR: Synchronous write indicator signal

t1, t2, t3, t4, ti1, ti2: time point

FIG. 1 is a schematic circuit diagram of a pseudo-static random access memory according to the first embodiment of the invention.

FIG. 2 is a timing diagram of the write operation according to the first embodiment.

3 is a schematic circuit diagram of an asynchronous controller according to the first embodiment Figure.

4 is a schematic circuit diagram of a clock generator according to the first embodiment.

FIG. 5 is a flowchart of the control method according to the first embodiment.

6 is a schematic circuit diagram of a control circuit according to a second embodiment of the invention.

7 is a timing diagram of a write operation according to the second embodiment.

8 is a schematic circuit diagram of a synchronous controller according to the second embodiment.

9 is a schematic circuit diagram of a clock generator according to the second embodiment.

10 is a flowchart of the control method according to the second embodiment.

Please refer to FIG. 1, which is a schematic circuit diagram of a pseudo-static random access memory according to a first embodiment of the present invention. In this embodiment, the pseudo-static random access memory 100 includes a memory array 110 and a control circuit 120. The controller 120 is used to provide row address strobe clock CASP to control the write operation of the memory array 110. The control circuit 120 includes a first counter 121, a second counter 122, a comparator 123, an asynchronous controller 124, and a clock generator 125. For example, the pseudo-static random access memory 100 further includes peripheral circuits such as input and output circuits and data latches. The first counter 121 is used to count the number of times the data written to the pseudo static random access memory 100 is latched based on the external clock, thereby generating a first count value N_DIN. The first counter 121 can count the number of data latches of the data latch based on the external clock CLK, thereby generating a first count value N_DIN. Once a data The latch latches the data. At this time, the first counter 121 will increment the first count value N_DIN according to the input indication signal EN_DIN, where the input indication signal EN_DIN is used to indicate the status signal of the input data. The second counter 122 is used to count the number of writes of the data written to the pseudo static random access memory 100 based on the asynchronous row address strobe clock CASP_A to generate a second count value N_DWR. The second counter 122 can count the number of times data is written to the memory array 110 based on the asynchronous row address strobe clock CASP_A, thereby generating a second count value N_DWR. Once the data is written to the memory array 110, the second counter 122 will increment the second count value N_DWR according to the write instruction signal EN_WR, where the write instruction signal EN_WR is a status signal used to indicate the execution of the write operation. The initial period of the asynchronous row address strobe clock CASP_A is less than the period of the external clock CLK. That is to say, during the writing operation, the data is written to the memory array 110 faster than the data is latched. Therefore, the increasing speed of the second count value N_DWR will be faster than the increasing speed of the first count value N_DIN.

The comparator 123 is coupled to the first counter 121 and the second counter 122. The comparator 123 compares the first count value N_DIN and the second count value N_DWR to determine whether the first count value N_DIN and the second count value N_DWR are equal. When the comparator 123 determines that the first count value N_DIN is equal to the second count value N_DWR, the mode signal ASYNC of the first logic level is provided. On the other hand, when the comparator 123 determines that the first count value N_DIN is not equal to the second count value N_DWR, the mode signal ASYNC of the second logic level is provided.

The asynchronous controller 124 is coupled to the comparator 123. Asynchronous controller 124 Used to receive the first logic level mode signal ASYNC and the row address strobe clock CASP during the write operation, and provide the asynchronous row address strobe according to the row address strobe clock CASP in the asynchronous mode Pulse CASP_A. When the asynchronous controller 124 receives the first logic level mode signal ASYNC for the first time, the write operation is changed from the asynchronous mode to the synchronous mode, so as to adjust the period of the asynchronous row address strobe clock CASP_A to The period of the external clock. The clock generator 125 is coupled to the asynchronous controller 124. The clock generator 125 is used to provide the row address strobe clock CASP according to the asynchronous row address strobe clock CASP_A.

Specifically, please refer to FIG. 1 and FIG. 2 at the same time. FIG. 2 is a timing diagram of the write operation according to the first embodiment. In this embodiment, at the time point t1, the data DQ starts to be input. And the input indication signal EN_DIN used to indicate that the data DQ is input is changed from a low logic level to a high logic level. At time t2, the first data D00 starts to be latched, and the first counter 121 starts to count the number of times the data DQ is latched based on the external clock CLK to generate a first count value N_DIN of "0". At this time, since the second count value N_DWR has not yet been generated, the first count value N_DIN and the second count value N_DWR are different. Therefore, the comparator 123 starts to provide the mode signal ASYNC of the second logic level (ie, high logic level) at time t2. Next, at time t3, the write operation starts. The write instruction signal EN_WR used to indicate the execution of the write operation changes from a low logic level to a high logic level. At time t3, the asynchronous controller 124 begins to provide the asynchronous row address strobe CASP_A when entering the write operation. Since the initial period of the asynchronous row address strobe clock CASP_A is less than the period of the external clock CLK, the control circuit 120 Enter the asynchronous mode of the write operation. The second counter 122 starts to count the number of writes of data written to the pseudo static random access memory 100 based on the asynchronous row address strobe clock CASP_A to generate a second count value N_DWR of “0”. In addition, the clock generator 125 provides the row address strobe clock CASP according to the asynchronous row address strobe clock CASP_A. Next, the first counter 121 and the second counter 122 continue to count. Since the increasing speed of the second count value N_DWR will be faster than the increasing speed of the first count value N_DIN. Therefore, at the time point t4, the second count value N_DWR is equal to the first count value N_DIN (N_DWR=N_DIN=8). This means that at time t4, the previously latched data D00~D08 are all written. The comparator 123 provides the mode signal ASYNC of the first logic level (ie, low logic level). It should be noted that this is when the asynchronous controller 124 receives the mode signal ASYNC of the first logic level for the first time in the write operation (the write instruction signal EN_WR is a high logic level), the The synchronization mode enters the synchronization mode. The asynchronous controller 124 does not provide an asynchronous row address strobe clock CASP_A according to the first logic level mode signal ASYNC. Subsequently, when the first count value N_DIN is equal to 9 and the second count value N_DWR is equal to 8, the mode signal ASYNC changes from the first logic level to the second logic level. At this time, the asynchronous controller 124 provides the asynchronous row address strobe clock CASP_A. In this way, the period of the asynchronous row address strobe clock CASP_A is gradually adjusted to the period of the external clock CLK, so as to achieve the effect of synchronizing the asynchronous row address strobe clock CASP_A with the external clock CLK. After time t4, the latch and write of data D09~D13 are synchronized until the pseudo-static random access memory becomes standby.

It is worth mentioning here that in the asynchronous mode, the control circuit 120 provides the asynchronous row address strobe clock CASP_A according to the row address strobe clock CASP to provide the row address strobe clock CASP. When the first count value N_DIN is equal to the second count value N_DWR for the first time, the control circuit 120 changes the write operation from the asynchronous mode to the synchronous mode to adjust the cycle of the asynchronous row address strobe clock CASP_A to the outside The period of the pulse is to provide the row address strobe clock CASP. In this way, the present invention can perform the synchronous mode and the asynchronous mode of the write operation without using multiple control paths during the write operation.

Next, the implementation details of the asynchronous controller will be described. Please refer to FIGS. 1 and 3 at the same time. FIG. 3 is a schematic circuit diagram of the asynchronous controller according to the first embodiment. In this embodiment, the asynchronous controller 124 includes a timing adjuster 1242 and an asynchronous determiner 1244. The timing adjuster 1242 is coupled to the clock generator 125. The timing adjuster 1242 is used to receive the row address strobe clock CASP, and adjust the time length of the low logic level of the asynchronous row address strobe clock CASP_A based on the row address strobe clock CASP. The asynchronous determinator 1244 is coupled to the timing adjuster 1242 and the comparator 123. The asynchronous determiner 1244 is used to provide an asynchronous row address strobe clock CASP_A when the mode signal ASYNC of the second logic level and the write enable signal EN_WR corresponding to the write operation are received.

In this embodiment, the timing adjuster 1242 includes inverters N01, N02, a delay D1, and an NAND gate NAND1. The input terminal of the inverter N01 is coupled to the clock generator 125 to receive the row address strobe clock CASP. The input terminal of the delay D1 is coupled to the output terminal of the inverter N01. The first input terminal of the NAND1 is coupled to The output terminal of the inverter N01 and the second input terminal of the inverter NAND1 are coupled to the output terminal of the delay D1. The input terminal of the inverter N02 is coupled to the output terminal of the NAND gate NAND1, and the output terminal of the inverter N02 is coupled to the asynchronous judgment unit 1244. The output terminal of the inverter N02 is used to output the asynchronous row address strobe clock CASP_A. In this embodiment, the timing adjuster 1242 can determine the time length of the low logic level of the asynchronous row address strobe clock CASP_A by the time delay setting of the delay D1.

The asynchronous determinator 1244 includes an NAND gate NAND2 and an inverter N03. The first input terminal of the NAND gate NAND2 is coupled to the inverter N02 of the timing regulator 1242. The second input terminal of the NAND gate NAND2 is used to receive the mode signal ASYNC. The third input terminal of the NAND gate NAND2 is used to receive the write enable signal EN_WR. The input terminal of the inverter N03 is coupled to the output terminal of the NAND gate NAND2. The output terminal of the inverter N03 is used to provide an asynchronous row address strobe clock CASP_A. The asynchronous determinator 1244 provides the asynchronous row address strobe clock CASP_A when it receives the write enable signal EN_WR of the high logic level and the mode signal ASYNC of the high logic level.

Next, the implementation details of the clock generator will be described. Please refer to FIGS. 1, 3 and 4 at the same time. FIG. 4 is a schematic circuit diagram of the clock generator according to the first embodiment. In this embodiment, the clock generator 125 includes inverters N04 and N05, flip-flops 1252, and timing adjusters 1254 and 1256. The input terminal of the inverter N04 is coupled to the asynchronous controller 124 to receive the asynchronous row address strobe clock CASP_A. The setting input terminal /S of the flip-flop 1252 is coupled to the output terminal of the inverter N04. The input terminal of the timing regulator 1254 is coupled to the output terminal Q of the flip-flop 1252. Inverter N05 The input terminal of is coupled to the output terminal of the timing adjuster 1254. The output of the inverter N05 is used to provide row address strobe clock CASP. The input of the timing adjuster 1256 is coupled to the output of the timing adjuster 1254. The output terminal of the timing regulator 1256 is coupled to the reset input terminal /R of the flip-flop 1252. The timing adjuster 1256 may adjust the reset timing of the flip-flop 1252 based on the row address strobe clock CASP. The flip-flop 1252 of this embodiment may be, for example, a set-reset (SR) latch composed of multiple flip-flops, and the present invention is not limited thereto.

Further, the timing adjuster 1254 includes a delay D2, an inverter N06, and an inverter NAND2. The input terminal of the delay D2 is coupled to the output terminal Q of the flip-flop 1252. The input terminal of the inverter N06 is coupled to the output terminal of the delay D2. The first input terminal of the NAND gate NAND2 is coupled to the output terminal Q of the flip-flop 1252. The second input terminal of the NAND gate NAND2 is coupled to the output terminal of the inverter N06. The output terminal of the NAND gate NAND2 is coupled to the input terminal of the inverter N05.

In this embodiment, under the cooperative operation of the asynchronous controller 124 and the clock generator 125, the timing adjuster 1254 can determine the asynchronous row address strobe clock CASP_A by the time delay setting of the delay D2 The length of time for the high logic level (ie, pulse width). In addition, in the timing adjuster 1242 of the asynchronous controller 124, the time delay setting of the delay D1 also indirectly determines the length of the low logic level of the row address strobe clock CASP.

The timing adjuster 1256 includes a delay D3, an inverter N07, and an inverter NAND3. The input of the delay D3 is coupled to the output of the timing adjuster 1254. The input terminal of the inverter N07 is coupled to the output terminal of the delay D3. Back gate The first input terminal of NAND3 is coupled to the output terminal of the timing adjuster 1254. The second input terminal of the NAND gate NAND3 is coupled to the output terminal of the inverter N07. The output terminal of the NAND gate NAND3 is coupled to the reset input terminal /R of the flip-flop 1252. In this embodiment, the timing adjuster 1256 can be regarded as resetting the flip-flop 1252 at the time point of the falling edge of the row address strobe clock CASP.

The time length of the low logic level of the row address strobe clock CASP can be related to the length of time for precharging the data bus of the pseudo-static random access memory. Therefore, a suitable length of time for precharge can be determined by the time delay setting of the delay D1 inside the asynchronous controller 124. The time length of the high logic level of the row address strobe clock CASP can be related to the time length necessary for the data readout of the memory cell/the write operation of the memory cell. Therefore, a suitable read/write time can be determined by the time delay setting of the delay D2 inside the clock generator 125.

Please refer to FIGS. 1 and 5 at the same time. FIG. 5 is a flowchart of the control method according to the first embodiment. In this embodiment, in step S510, the control circuit 120 counts the number of latches of the data written to the pseudo static random access memory 100 based on the external clock CLK to generate the first count value N_DIN. In step S520, after generating the first count value N_DIN, the control circuit 120 provides the asynchronous row address strobe clock CASP_A according to the row address strobe clock CASP in the asynchronous mode. In step S530, the control circuit 120 counts the number of writes of data written to the pseudo static random access memory based on the asynchronous row address strobe clock CASP_A to generate a second count value N_DWR. The control circuit 120 compares the first count value N_DIN and the second count value N_DWR in step S540. In step S540, the control circuit 120 It is determined whether the first count value N_DIN is equal to the second count value N_DWR. If the control circuit 120 determines that the first count value N_DIN is not equal to the second count value N_DWR, it maintains the asynchronous mode and proceeds to step S550. In step S550, the control circuit 120 provides the row address strobe clock CASP according to the asynchronous row address strobe clock CASP_A. In step S540, if the control circuit 120 determines that the first count value N_DIN is equal to the second count value N_DWR, it proceeds to step S560 to provide the first logic level mode signal ASYNC, and proceeds to step S570. In step S570, the control circuit 120 shifts the write operation from the asynchronous mode to the synchronous mode according to the mode signal ASYNC of the first logic level provided for the first time, so as to gate the cycle of the asynchronous line address CASP_A Adjust to the period of the external clock, and go to step S550. The implementation details of steps S510-S570 are described in detail in the foregoing embodiments and implementations, so they will not be repeated here.

Please refer to FIG. 6, which is a schematic circuit diagram of a control circuit according to a second embodiment of the present invention. In this embodiment, the control circuit 620 is used to provide row address strobe clock CASP to control the write operation of the memory array (not shown) of the pseudo static random access memory. The control circuit 620 includes a first counter 621, a second counter 622, a comparator 623, an asynchronous controller 624, a clock generator 625, a synchronous write indicator 626, and a synchronous controller 627. The implementation details of the cooperative operation among the first counter 621, the second counter 622, the comparator 623, and the asynchronous controller 624 can be sufficiently taught in the first embodiment, and therefore will not be repeated here. In this embodiment, the synchronous write indicator 626 is used to determine whether the first initial time point for the pseudo static random access memory to perform the write operation is earlier than the write to the pseudo static The second initial time point for the data of the state random access memory to be latched. When the synchronous write indicator 626 determines that the first initial time point is earlier than the second initial time point, it provides the synchronous write instruction signal SYNCWR. On the other hand, when the synchronous write indicator 626 determines that the first initial time point is later than or equal to the second initial time point, the synchronous write indication signal SYNCWR is not provided. The synchronization controller 627 is coupled to the synchronization write indicator 626 and the clock generator 625. The synchronization controller 627 is used to enable the synchronization row address gating based on the external clock CLK according to the synchronization write instruction signal SYNCWR Pulse CASP_S. When the clock generator 625 receives the sync row address strobe clock CASP_S, it will provide the row address strobe clock CASP according to the sync row address strobe clock CASP_S.

Specifically, please refer to Figure 6 and Figure 7 at the same time. 7 is a timing diagram of a write operation according to the second embodiment. In this embodiment, the first initial time point is the time point ti1 at which the write instruction signal EN_WR is used to instruct the write operation to transition from the low logic level to the high logic level for the first time. The second initial time point is the time point ti2 at which the input indication signal EN_DIN for indicating that the data DQ is input is transitioned from the low logic level to the high logic level for the first time. When the synchronous write indicator 626 determines that the first initial time point (time point ti1) is earlier than the second initial time point (time point ti2), it provides the synchronous write instruction signal SYNCWR. In this embodiment, the synchronous write indicator 626 is also coupled to the first counter 621 and the second counter 622. When the time point ti1 is earlier than the time point ti2, the first counter 621 is disabled according to the synchronous write instruction signal SYNCWR to stop providing the first count value N_DIN, and the second counter 622 is disabled according to the synchronous write instruction signal SYNCWR Can stop providing second The count value N_DWR, so the comparator 623 does not provide the second logic level mode signal ASYNC. This makes the asynchronous controller 624 unable to provide the asynchronous row address strobe clock CASP_A. In addition, the synchronization controller 627 is enabled according to the synchronization write instruction signal SYNCWR to provide the synchronization row address strobe clock CASP_S, thereby generating the row address strobe clock CASP. The period of the strobe clock CASP_S with the same walking address is equal to the period of the external clock CLK.

On the other hand, when the synchronous write indicator 626 determines that the first initial time point (time point ti1) is earlier than the second initial time point (time point ti2), the synchronous write indication signal SYNCWR is not provided. In the case where the synchronous write instruction signal SYNCWR is not provided. The first counter 621 can provide a first count value N_DIN, the second counter 622 can provide a second count value N_DWR, and the synchronization controller 627 is disabled. Regarding implementation details in the case where the synchronous write instruction signal SYNCWR is not provided, sufficient teaching can be obtained in the embodiments of FIG. 1 to FIG. 5, so it will not be repeated here.

It is worth mentioning here that the control circuit 620 of the second embodiment can also determine whether the time point at which the data DQ starts to be written is earlier than the start of the data DQ according to the first initial time point and the second initial time point described above The point in time when it was latched. If the time point at which the data DQ starts to be written is earlier than the time point at which the data DQ is latched, the control circuit 620 will provide the synchronized row address strobe clock CASP_S and provide the row according to the synchronized row address strobe clock CASP_S Address strobe clock CASP. In this way, the timing when the data DQ is latched will be synchronized with the timing when the data DQ is written, and it will not happen that the timing when the data DQ is latched cannot catch up with the timing when the data DQ is written condition.

Next, the implementation details of the synchronization controller will be described. Please refer to FIG. 6 and FIG. 8 at the same time. FIG. 8 is a schematic circuit diagram of the synchronization controller according to the second embodiment. In this embodiment, the synchronization controller 627 includes an NAND gate NAND4 and an inverter N07. The first input terminal of the NAND gate NAND4 is used to receive the external clock CLK. The second input terminal of the NAND gate NAND4 is used to receive the input indication signal EN_DIN. The second input terminal of the NAND gate NAND4 is used to receive the synchronous write instruction signal SYNCWR provided by the synchronous write indicator 626. The input terminal of the inverter N07 is coupled to the output terminal of the NAND gate NAND4. The output terminal of the inverter N07 is used to provide the synchronization row address strobe clock CASP_S to the clock generator 625.

Next, the implementation details of the clock generator will be described. Please refer to FIG. 6 and FIG. 9 at the same time. FIG. 9 is a circuit diagram of the clock generator according to the second embodiment. In this embodiment, the clock generator 625 includes inverters N08, N09, flip-flops 6252, and timing adjusters 6254, 6256, 6258. The input terminal of the inverter N08 is coupled to the asynchronous controller 624 to receive the asynchronous row address strobe clock CASP_A. The first setting input terminal /S1 of the flip-flop 6252 is coupled to the output terminal of the inverter N08. The input terminal of the timing adjuster 6254 is coupled to the output terminal Q of the flip-flop 6252. The timing adjuster 6254 may be the same as the timing adjuster 1254 of FIG. 4 or a simple change to the timing adjuster 1254 of FIG. 4. The input terminal of the inverter N09 is coupled to the output terminal of the timing adjuster 6254. The output terminal of the inverter N09 is used to provide row address strobe clock CASP. The input of the timing adjuster 6256 is coupled to the output of the timing adjuster 6254. The output terminal of the timing regulator 6256 is coupled to the flip-flop 6252 reset input /R. The timing adjuster 6256 may be the same as the timing adjuster 1254 of FIG. 4 or a simple change to the timing adjuster 1256 of FIG. 4. The timing adjuster 6256 can adjust the reset timing of the flip-flop 6252 based on the row address strobe clock CASP. The input terminal of the timing adjuster 6258 is coupled to the synchronization controller 627 to receive the synchronization row address strobe clock CASP_S. The output terminal of the timing regulator 6258 is coupled to the second setting input terminal /S2 of the flip-flop 6252. The flip-flop 6252 of this embodiment may be, for example, a set-reset (SR) latch composed of multiple flip-flops, and the present invention is not limited thereto.

The timing adjuster 6258 includes a delay D4, an inverter N10, and an inverter NAND5. The input terminal of the delay D4 is coupled to the synchronization controller 627 to receive the synchronization row address strobe clock CASP_S. The input terminal of the inverter N10 is coupled to the output terminal of the delay D4. The first input terminal of the NAND gate NAND5 is coupled to the synchronization controller 627 to receive the synchronization row address strobe clock CASP_S. The second input terminal of the NAND gate NAND2 is coupled to the output terminal of the inverter N10. The output terminal of the NAND gate NAND2 is coupled to the second setting input terminal /S2 of the flip-flop 6252.

Please refer to FIGS. 6 and 10 at the same time. FIG. 10 is a flowchart of the control method according to the second embodiment. In this embodiment, in step S1010, the control circuit receives the first initial time point at which the pseudo static random access memory performs the write operation and the second initial time to latch the data written to the pseudo static random access memory Point in time. The control circuit 620 determines in step S1020 whether it is earlier than the second initial time point for latching the data written to the pseudo static random access memory. When it is determined that the first initial time point is earlier than the second initial time point, the control circuit 620 provides synchronous writing Instruct the signal SYNCWR, and proceed to step S1030. In step S1030, the control circuit 620 provides the synchronization row address strobe clock CASP_S based on the external clock according to the synchronization write instruction signal SYNCWR. Next, in step S1040, the row address strobe clock CASP is provided according to the synchronized row address strobe clock CASP_S. The implementation details of steps S1010 to S1040 are described in detail in the foregoing embodiments and implementations, and therefore will not be repeated here. On the other hand, when the control circuit 620 determines in step S1020 that the first initial time point is later than or equal to the second initial time point, it does not provide the synchronous write instruction signal SYNCWR, and proceeds to step S510 of FIG. 5. After the control circuit 620 enters step S510, the control method of the control circuit 620 will be the same as the control method of the control circuit 120 of FIG. 1 (steps S510-S570).

In summary, the control circuit and control method of the present invention count the number of data latches based on an external clock to generate a first count value, and count the number of data writes based on an asynchronous line address strobe clock To generate a second count value, and compare the first count value with the second count value. The control circuit and the control method provide the non-synchronized row address strobe clock according to the row address strobe clock in the asynchronous mode to provide the row address strobe clock. When the first count value is equal to the second count value for the first time, the control circuit and the control method change the write operation from the asynchronous mode to the synchronous mode to adjust the period of the asynchronous row address strobe clock to the external clock To provide the row address strobe clock. In this way, the present invention can perform the synchronous mode and the asynchronous mode of the write operation without using multiple control paths during the write operation. In addition, the control circuit and control method of the present invention can also determine whether the time when the data starts to be written is earlier than the time when the data starts to be latched. If the information is open Whether the time when the data is written is earlier than the time when the data is latched, the control circuit and the control method will provide the synchronization row address strobe clock and provide the row address strobe according to the synchronization row address strobe clock Clock. In this way, the timing when the data is latched will be synchronized with the timing when the data is written, and it will not happen that the timing when the data is latched cannot catch up with the timing when the data is written.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

The invention relates to a control circuit and a control method for pseudo-static random access memory. The control circuit and the control method can support the write operation in the asynchronous mode and the write operation in the synchronous mode.

100: pseudo-static random access memory

110: memory array

120: control circuit

121: First counter

122: second counter

123: Comparator

124: Asynchronous controller

125: clock generator

ASYNC: mode signal

CASP: row address strobe clock

CASP_A: Asynchronous row address strobe clock

CLK: external clock

EN_DIN: input indicator signal

EN_WR: write indicator signal

N_DIN: first count value

N_DWR: second count value

Claims (18)

A control circuit suitable for a pseudo-static random access memory, the control circuit includes: a first counter for latching the number of data written to the pseudo-static random access memory based on an external clock Count to generate a first count value; a second counter to count the number of writes of data written to the pseudo-static random access memory based on an asynchronous row address strobe clock, To generate a second count value, wherein the initial period of the asynchronous row address strobe clock is less than the period of the external clock; a comparator, coupled to the first counter and the second counter, is used to compare the A first count value and a second count value, when the first count value is equal to the second count value, a mode signal of a first logic level is provided; and an asynchronous controller is coupled to the comparator, It is used to receive the mode signal and the row address strobe clock in a write operation, and to provide the asynchronous row address strobe clock according to the row address strobe clock in an asynchronous mode. When the synchronous controller receives the mode signal of the first logic level for the first time, the write operation enters a synchronous mode from the asynchronous mode to adjust the period of the asynchronous row address strobe clock to the The period of the external clock; and a clock generator, coupled to the asynchronous controller, for providing the row address strobe according to the asynchronous row address strobe. The control circuit as described in item 1 of the patent application scope, wherein when the first count value is not equal to the second count value, the comparator provides the mode signal of a second logic level, wherein the second logic level The bit is different from the first logic level. The control circuit as described in item 2 of the patent application scope, wherein when the mode signal of the second logic level is provided, the asynchronous controller starts to provide the asynchronous row address strobe when entering the write operation pulse. The control circuit according to any one of items 1 to 3 of the patent application range, wherein the asynchronous controller includes: a first timing regulator coupled to the clock generator to receive the Row address strobe clock, and adjust the time length of the low logic level of the asynchronous row address strobe clock based on the row address strobe clock; and an asynchronous determinator coupled to the first The timing adjuster and the comparator are used to provide the asynchronous row address strobe when the mode signal of the second logic level and the write enable signal corresponding to the write operation are received pulse. The control circuit as described in item 4 of the patent application scope, wherein the first timing regulator includes: a first inverter, an input terminal of the first inverter is coupled to the clock generator to receive the Row address strobe clock; a delay, the input of the delay is coupled to the output of the first inverter; an inverting gate, the first input of the inverting gate is coupled to the first An output terminal of an inverter, the second input terminal of the inverter gate is coupled to the output terminal of the delay; and a second inverter, the input terminal of the second inverter is coupled to the inverter and Gate At the output, the output of the second inverter is coupled to the asynchronous determinator. The control circuit according to any one of items 1 to 3 of the patent application scope, wherein the clock generator includes: a first inverter, and an input terminal of the first inverter is coupled to the non-inverter The synchronous controller receives the non-synchronous row address strobe clock; a flip-flop, the setting input of the flip-flop is coupled to the output of the first inverter; a first timing regulator, the The input terminal of the first timing regulator is coupled to the output terminal of the flip-flop. The first timing regulator is used to adjust the high logic of the row address strobe clock based on the asynchronous row address strobe clock The length of time for the level; a second inverter, the input of the second inverter is coupled to the output of the first timing regulator, and the output of the second inverter is used to provide the row Address strobe clock; and a second timing adjuster, the input of the second timing adjuster is coupled to the output of the first timing adjuster, and the output end of the second timing adjuster is coupled to At the reset input terminal of the flip-flop, the second timing adjuster is used to adjust the reset timing of the flip-flop based on the strobe clock of the asynchronous row address. The control circuit as described in item 1 of the patent application scope further includes: a synchronous write indicator for determining whether a first initial time point at which the pseudo static random access memory performs the write operation is earlier than A second initial time point for latching the data written to the pseudo-static random access memory, and When it is determined that the first initial time point is earlier than the second initial time point, a synchronous write indication signal is provided; and a synchronous controller, coupled to the synchronous write indicator and the clock generator, is used to In accordance with the synchronous writing instruction signal, it is enabled to provide a strobe clock based on the external clock. The control circuit as described in item 7 of the patent application range, wherein the first counter is disabled according to the synchronous write instruction signal to stop providing the first count value, and the second counter is disabled according to the synchronous write instruction signal The second count value can be stopped to enable the comparator to provide the mode signal of the first logic level. The control circuit as described in item 7 of the patent application scope, wherein the clock generator is also used to provide the row address strobe according to the synchronous row address strobe when the synchronous write instruction signal is provided pulse. The control circuit as described in item 7 of the patent application scope, wherein the clock generator includes: a first inverter, an input terminal of the first inverter is coupled to the asynchronous controller to receive the asynchronous line position Address strobe clock; a flip-flop, the first setting input of the flip-flop is coupled to the output of the first inverter; a first timing regulator, the first timing regulator The input terminal is coupled to the output terminal of the flip-flop; a second inverter, the input terminal of the second inverter is coupled to the output terminal of the first timing regulator, the The output terminal is used to provide the row address strobe Pulse; and a second timing adjuster, the input of the second timing adjuster is coupled to the output of the first timing adjuster, and the output of the second timing adjuster is coupled to the A reset input terminal, the second timing adjuster is used to adjust the reset timing of the flip-flop based on the non-synchronized row address strobe clock; and a third timing adjuster, the input terminal of the third timing adjuster is coupled Connected to the synchronous controller to receive the synchronous row address strobe clock, the input terminal of the third timing regulator is coupled to the second setting input terminal of the flip-flop. A control method applicable to a pseudo-static random access memory. The control method includes: counting the number of latches of data written to the pseudo-static random access memory based on an external clock to generate a first A count value; providing an asynchronous row address strobe clock according to the row address strobe clock in an asynchronous mode; writing the pseudo-random access memory based on the asynchronous row address strobe clock pair The number of times of writing data of the body is counted to generate a second count value, wherein the initial period of the asynchronous row address strobe clock is less than the period of the external clock; compare the first count value with the second count Value, wherein a mode signal providing a first logic level is provided when the first count value is equal to the second count value; the write operation is performed according to the mode signal of the first logic level provided for the first time Enter a synchronous mode from the asynchronous mode to adjust the period of the asynchronous row address strobe clock to the period of the external clock; and The row address strobe clock is provided based on the asynchronous row address strobe clock. The control method as described in item 11 of the patent application scope, wherein the step of comparing the first count value with the second count value includes: when the first count value is not equal to the second count value, providing a second logic The mode signal of the level, wherein the second logic level is different from the first logic level. The control method as described in item 12 of the patent application scope, which further includes: when the mode signal of the second logic level is provided, starting to provide the asynchronous row address strobe clock when entering the write operation . The control method as described in any one of claims 11 to 13, wherein the step of providing the non-synchronized row address strobe clock in the asynchronous mode according to the row address strobe clock includes : Receive the row address strobe clock, and adjust the time length of the low logic level of the asynchronous row address strobe clock based on the row address strobe clock; and when the second logic level is received The mode signal and the write enable signal corresponding to entering the write operation should provide an asynchronous row address strobe clock. The control method according to any one of items 11 to 13 of the patent application range, wherein the step of providing the row address strobe clock according to the asynchronous row address strobe clock includes: based on the asynchronous The row address strobe clock adjusts the time length of the high logic level of the row address strobe clock. The control method described in item 11 of the patent application scope also includes: Determining whether a first initial time point at which the pseudo static random access memory performs the write operation is earlier than a second initial time point at which data written to the pseudo static random access memory is latched; When it is determined that the first initial time point is earlier than the second initial time point, a synchronous write instruction signal is provided; and a walk-in address strobe clock is provided based on the external clock according to the synchronous write instruction signal. The control method as described in item 16 of the patent application scope further includes: stopping providing the first count value according to the synchronous writing instruction signal and stopping providing the second count value according to the synchronous writing instruction signal to provide the first The logic level of this mode signal. The control method as described in Item 16 of the patent application scope further includes: when the synchronous write instruction signal is provided, providing the row address strobe clock according to the synchronous row address strobe clock.

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