JP6816046B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
JP6816046B2
JP6816046B2 JP2018019434A JP2018019434A JP6816046B2 JP 6816046 B2 JP6816046 B2 JP 6816046B2 JP 2018019434 A JP2018019434 A JP 2018019434A JP 2018019434 A JP2018019434 A JP 2018019434A JP 6816046 B2 JP6816046 B2 JP 6816046B2
Authority
JP
Japan
Prior art keywords
support substrate
manufacturing
semiconductor device
layer
peripheral portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018019434A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019140150A (ja
JP2019140150A5 (cg-RX-API-DMAC10.html
Inventor
河野　一郎
一郎 河野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aoi Electronics Co Ltd
Original Assignee
Aoi Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2018019434A priority Critical patent/JP6816046B2/ja
Application filed by Aoi Electronics Co Ltd filed Critical Aoi Electronics Co Ltd
Priority to CN201980011621.0A priority patent/CN111684585A/zh
Priority to PCT/JP2019/003169 priority patent/WO2019155959A1/ja
Priority to KR1020207019198A priority patent/KR102407800B1/ko
Priority to US16/967,480 priority patent/US11521948B2/en
Priority to TW108104296A priority patent/TWI802648B/zh
Publication of JP2019140150A publication Critical patent/JP2019140150A/ja
Publication of JP2019140150A5 publication Critical patent/JP2019140150A5/ja
Application granted granted Critical
Publication of JP6816046B2 publication Critical patent/JP6816046B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W78/00—Detachable holders for supporting packaged chips in operation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7412—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H10P72/7418—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. a chip mounting substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/744—Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
    • H10P72/7442—Separation by peeling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/241—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements
    • H10W44/248—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF] for passive devices or passive elements for antennas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07202—Connecting or disconnecting of bump connectors using auxiliary members
    • H10W72/07204—Connecting or disconnecting of bump connectors using auxiliary members using temporary auxiliary members, e.g. sacrificial coatings
    • H10W72/07207—Temporary substrates, e.g. removable substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07211—Treating the bond pad before connecting, e.g. by applying flux or cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07232—Compression bonding, e.g. thermocompression bonding
    • H10W72/07233—Ultrasonic bonding, e.g. thermosonic bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Dicing (AREA)
  • Bipolar Transistors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
JP2018019434A 2018-02-06 2018-02-06 半導体装置の製造方法 Active JP6816046B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2018019434A JP6816046B2 (ja) 2018-02-06 2018-02-06 半導体装置の製造方法
PCT/JP2019/003169 WO2019155959A1 (ja) 2018-02-06 2019-01-30 半導体装置の製造方法
KR1020207019198A KR102407800B1 (ko) 2018-02-06 2019-01-30 반도체 장치의 제조 방법
US16/967,480 US11521948B2 (en) 2018-02-06 2019-01-30 Method of manufacturing semiconductor device
CN201980011621.0A CN111684585A (zh) 2018-02-06 2019-01-30 半导体装置的制造方法
TW108104296A TWI802648B (zh) 2018-02-06 2019-02-01 半導體裝置之製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018019434A JP6816046B2 (ja) 2018-02-06 2018-02-06 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2019140150A JP2019140150A (ja) 2019-08-22
JP2019140150A5 JP2019140150A5 (cg-RX-API-DMAC10.html) 2019-11-28
JP6816046B2 true JP6816046B2 (ja) 2021-01-20

Family

ID=67547988

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018019434A Active JP6816046B2 (ja) 2018-02-06 2018-02-06 半導体装置の製造方法

Country Status (6)

Country Link
US (1) US11521948B2 (cg-RX-API-DMAC10.html)
JP (1) JP6816046B2 (cg-RX-API-DMAC10.html)
KR (1) KR102407800B1 (cg-RX-API-DMAC10.html)
CN (1) CN111684585A (cg-RX-API-DMAC10.html)
TW (1) TWI802648B (cg-RX-API-DMAC10.html)
WO (1) WO2019155959A1 (cg-RX-API-DMAC10.html)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020131552A (ja) * 2019-02-20 2020-08-31 株式会社東芝 キャリアおよび半導体装置の製造方法
JP7362378B2 (ja) * 2019-09-12 2023-10-17 株式会社東芝 キャリア及び半導体装置の製造方法
JP7395898B2 (ja) * 2019-09-18 2023-12-12 大日本印刷株式会社 半導体多面付け基板用部材、半導体多面付け基板、および半導体部材
CN112786513B (zh) * 2019-11-11 2023-06-09 上海新微技术研发中心有限公司 一种薄膜器件的加工方法及薄膜器件
CN112786515B (zh) * 2019-11-11 2022-12-13 上海新微技术研发中心有限公司 一种薄膜器件的加工方法
JP7474608B2 (ja) * 2020-03-09 2024-04-25 アオイ電子株式会社 半導体装置の製造方法、および半導体封止体
JP7521258B2 (ja) * 2020-05-26 2024-07-24 Ｔｏｐｐａｎホールディングス株式会社 基板ユニット、基板ユニットの製造方法及び半導体装置の製造方法
JP6985477B1 (ja) * 2020-09-25 2021-12-22 アオイ電子株式会社 半導体装置および半導体装置の製造方法
KR102684002B1 (ko) * 2020-12-14 2024-07-11 주식회사 네패스 반도체 패키지 제조방법 및 이에 이용되는 가이드 프레임
EP4586310A4 (en) * 2022-09-05 2025-12-10 Mitsui Mining & Smelting Co Ltd Printed circuit board manufacturing process
JP2024090052A (ja) * 2022-12-22 2024-07-04 ローム株式会社 半導体装置およびそれを含む半導体パッケージ

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56158480A (en) 1980-05-12 1981-12-07 Nippon Telegr & Teleph Corp <Ntt> Field effect transistor
JP3455762B2 (ja) * 1999-11-11 2003-10-14 カシオ計算機株式会社 半導体装置およびその製造方法
JP2004134672A (ja) * 2002-10-11 2004-04-30 Sony Corp 超薄型半導体装置の製造方法および製造装置、並びに超薄型の裏面照射型固体撮像装置の製造方法および製造装置
JP2006222164A (ja) * 2005-02-08 2006-08-24 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP4103896B2 (ja) * 2005-03-16 2008-06-18 ヤマハ株式会社 半導体装置の製造方法および半導体装置
JP2009147270A (ja) * 2007-12-18 2009-07-02 Nec Electronics Corp 配線基板の製造方法、配線基板、および半導体装置
JP2010251682A (ja) * 2009-03-26 2010-11-04 Kyocera Corp 多数個取り配線基板
JP5042297B2 (ja) * 2009-12-10 2012-10-03 日東電工株式会社 半導体装置の製造方法
JP2011204765A (ja) * 2010-03-24 2011-10-13 Toshiba Corp 半導体装置の製造方法及び半導体装置
US8507322B2 (en) * 2010-06-24 2013-08-13 Akihiro Chida Semiconductor substrate and method for manufacturing semiconductor device
JP5458029B2 (ja) * 2011-01-19 2014-04-02 日本特殊陶業株式会社 多数個取り配線基板
JP5225451B2 (ja) * 2011-11-04 2013-07-03 新光電気工業株式会社 配線基板の製造方法及び半導体パッケージの製造方法
JP2016134497A (ja) * 2015-01-19 2016-07-25 凸版印刷株式会社 配線基板積層体及びこれを用いた半導体装置の製造方法
JP6511695B2 (ja) * 2015-01-20 2019-05-15 ローム株式会社 半導体装置およびその製造方法
JP2017017238A (ja) * 2015-07-03 2017-01-19 株式会社ジェイデバイス 半導体装置及びその製造方法
WO2017149810A1 (ja) * 2016-02-29 2017-09-08 三井金属鉱業株式会社 キャリア付銅箔及びその製造方法、並びに配線層付コアレス支持体及びプリント配線板の製造方法
JP2017162876A (ja) 2016-03-07 2017-09-14 株式会社ジェイデバイス 半導体パッケージの製造方法

Also Published As

Publication number Publication date
US11521948B2 (en) 2022-12-06
TWI802648B (zh) 2023-05-21
TW201935576A (zh) 2019-09-01
KR20200094780A (ko) 2020-08-07
US20210217719A1 (en) 2021-07-15
WO2019155959A1 (ja) 2019-08-15
JP2019140150A (ja) 2019-08-22
KR102407800B1 (ko) 2022-06-10
CN111684585A (zh) 2020-09-18

Similar Documents

Publication Publication Date Title
KR102407800B1 (ko) 반도체 장치의 제조 방법
US8209856B2 (en) Printed wiring board and method for manufacturing the same
JP5599276B2 (ja) 半導体素子、半導体素子実装体及び半導体素子の製造方法
JP3983146B2 (ja) 多層配線基板の製造方法
CN1941339B (zh) 嵌入有半导体ic的基板及其制造方法
JP5902931B2 (ja) 配線基板の製造方法、及び、配線基板製造用の支持体
JP6029958B2 (ja) 配線基板の製造方法
JP2000216330A (ja) 積層型半導体装置およびその製造方法
JP7347440B2 (ja) 半導体パッケージ用配線基板の製造方法
US8766101B2 (en) Wiring substrate, method for manufacturing wiring substrate, and semiconductor package including wiring substrate
JP4121542B1 (ja) 電子装置の製造方法
JP4219951B2 (ja) はんだボール搭載方法及びはんだボール搭載基板の製造方法
TW201110267A (en) An electronic device package and method of manufacture
TW202230638A (zh) 附支持體之基板單元、基板單元、及附支持體之基板單元的製造方法
JP2007242888A (ja) 半導体パッケージ製造方法
JP2008235555A (ja) 電子装置の製造方法及び基板及び半導体装置
JP2009117771A (ja) 半導体パッケージの製造方法
JP4483136B2 (ja) 半導体デバイスの実装方法及び半導体装置の製造方法
JP6534700B2 (ja) 半導体装置の製造方法
JP2016219646A (ja) 半導体装置及びその製造方法
JP2021190473A (ja) 基板ユニット、基板ユニットの製造方法及び半導体装置の製造方法
JP2011040610A (ja) 半導体装置及びその製造方法
JP2007250834A (ja) 電子部品装置の製造方法
JP2011109152A (ja) プリント配線板及びその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20191016

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20191016

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20191016

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20191204

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200121

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200312

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20200707

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200925

C60 Trial request (containing other claim documents, opposition documents)

Free format text: JAPANESE INTERMEDIATE CODE: C60

Effective date: 20200925

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20201005

C21 Notice of transfer of a case for reconsideration by examiners before appeal proceedings

Free format text: JAPANESE INTERMEDIATE CODE: C21

Effective date: 20201006

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20201222

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20201223

R150 Certificate of patent or registration of utility model

Ref document number: 6816046

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250