JP6815237B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP6815237B2
JP6815237B2 JP2017051414A JP2017051414A JP6815237B2 JP 6815237 B2 JP6815237 B2 JP 6815237B2 JP 2017051414 A JP2017051414 A JP 2017051414A JP 2017051414 A JP2017051414 A JP 2017051414A JP 6815237 B2 JP6815237 B2 JP 6815237B2
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JP
Japan
Prior art keywords
insulating film
semiconductor device
peripheral region
region
element region
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JP2017051414A
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English (en)
Japanese (ja)
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JP2018157022A (ja
JP2018157022A5 (enExample
Inventor
徹雄 高橋
徹雄 高橋
政良 多留谷
政良 多留谷
和彦 作谷
和彦 作谷
原田　賢治
賢治 原田
正雄 高田
正雄 高田
幸一 因
幸一 因
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2017051414A priority Critical patent/JP6815237B2/ja
Priority to US15/837,387 priority patent/US10756029B2/en
Publication of JP2018157022A publication Critical patent/JP2018157022A/ja
Publication of JP2018157022A5 publication Critical patent/JP2018157022A5/ja
Priority to US16/895,837 priority patent/US11031357B2/en
Application granted granted Critical
Publication of JP6815237B2 publication Critical patent/JP6815237B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H10P54/90—Auxiliary processes or arrangements
    • H10P54/92—Auxiliary processes or arrangements for protecting or reinforcing the surface of wafers or substrates during cutting or separating, e.g. using adhesive tapes
    • H10P54/922—Arrangements for stress mitigation, e.g. crack stops
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/43—Encapsulations, e.g. protective coatings characterised by their materials comprising oxides, nitrides or carbides, e.g. ceramics or glasses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
    • H10W46/503—Located in scribe lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dicing (AREA)
JP2017051414A 2017-03-16 2017-03-16 半導体装置 Active JP6815237B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2017051414A JP6815237B2 (ja) 2017-03-16 2017-03-16 半導体装置
US15/837,387 US10756029B2 (en) 2017-03-16 2017-12-11 Semiconductor device
US16/895,837 US11031357B2 (en) 2017-03-16 2020-06-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017051414A JP6815237B2 (ja) 2017-03-16 2017-03-16 半導体装置

Publications (3)

Publication Number Publication Date
JP2018157022A JP2018157022A (ja) 2018-10-04
JP2018157022A5 JP2018157022A5 (enExample) 2019-07-18
JP6815237B2 true JP6815237B2 (ja) 2021-01-20

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Application Number Title Priority Date Filing Date
JP2017051414A Active JP6815237B2 (ja) 2017-03-16 2017-03-16 半導体装置

Country Status (2)

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US (2) US10756029B2 (enExample)
JP (1) JP6815237B2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7443097B2 (ja) * 2020-03-09 2024-03-05 キオクシア株式会社 半導体ウェハおよび半導体チップ
WO2021240603A1 (ja) 2020-05-25 2021-12-02 三菱電機株式会社 半導体装置、および、半導体装置の製造方法
JP7638197B2 (ja) * 2021-11-19 2025-03-03 三菱電機株式会社 半導体ウエハおよび半導体ウエハの製造方法
FR3131799B1 (fr) * 2022-01-10 2024-12-20 St Microelectronics Crolles 2 Sas Procédé de fabrication de circuits intégrés à partir d’une plaquette en substrat semiconducteur
US12224248B2 (en) * 2022-03-07 2025-02-11 SanDisk Technologies, Inc. Semiconductor wafer and semiconductor dies formed therefrom including grooves along long edges of the semiconductor dies

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61251147A (ja) * 1985-04-30 1986-11-08 Oki Electric Ind Co Ltd 半導体ウエハのチツプ分割方法
JPS6424442A (en) * 1987-07-20 1989-01-26 Mitsubishi Electric Corp Semiconductor wafer
JP2777426B2 (ja) * 1989-10-16 1998-07-16 三洋電機株式会社 半導体装置の製造方法
JPH04251960A (ja) * 1991-01-09 1992-09-08 Fujitsu Ltd 半導体ウエハおよび半導体装置の製造方法
JP2776457B2 (ja) 1992-12-29 1998-07-16 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体デバイスのクラックストップ形成方法及び半導体デバイス
JPH06275713A (ja) 1993-03-19 1994-09-30 Hitachi Ltd 半導体ウエハおよび半導体チップならびにダイシング方法
JP2008053559A (ja) * 2006-08-25 2008-03-06 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2008085278A (ja) * 2006-09-29 2008-04-10 Ricoh Co Ltd 半導体装置及びその製造方法
JP5507118B2 (ja) * 2009-05-20 2014-05-28 富士電機株式会社 半導体装置およびその製造方法
JP5625558B2 (ja) * 2010-02-22 2014-11-19 サンケン電気株式会社 半導体ウェハ、及び半導体装置の製造方法
JP2011243859A (ja) * 2010-05-20 2011-12-01 Renesas Electronics Corp 半導体装置および半導体装置の製造方法
JP5633992B2 (ja) * 2010-06-11 2014-12-03 トヨタ自動車株式会社 半導体装置および半導体装置の製造方法
JP2013012652A (ja) 2011-06-30 2013-01-17 Fuji Electric Co Ltd 逆阻止絶縁ゲート型バイポーラトランジスタとその製造方法
JP6063629B2 (ja) * 2012-03-12 2017-01-18 ローム株式会社 半導体装置および半導体装置の製造方法
US8907408B2 (en) * 2012-03-26 2014-12-09 Infineon Technologies Austria Ag Stress-reduced field-effect semiconductor device and method for forming therefor
JP2014138143A (ja) * 2013-01-18 2014-07-28 Toyota Motor Corp 半導体装置の製造方法、半導体ウエハ、及び、半導体装置
JP6135528B2 (ja) * 2014-01-31 2017-05-31 三菱電機株式会社 半導体装置の製造方法
JP6299412B2 (ja) 2014-05-15 2018-03-28 三菱電機株式会社 半導体装置および半導体装置の製造方法
JP6274968B2 (ja) * 2014-05-16 2018-02-07 ローム株式会社 半導体装置
JP6589278B2 (ja) 2015-01-16 2019-10-16 富士電機株式会社 半導体素子および半導体素子の製造方法

Also Published As

Publication number Publication date
JP2018157022A (ja) 2018-10-04
US10756029B2 (en) 2020-08-25
US20180269162A1 (en) 2018-09-20
US20200303323A1 (en) 2020-09-24
US11031357B2 (en) 2021-06-08

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