JP2014138143A - 半導体装置の製造方法、半導体ウエハ、及び、半導体装置 - Google Patents
半導体装置の製造方法、半導体ウエハ、及び、半導体装置 Download PDFInfo
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- 230000002093 peripheral effect Effects 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 30
- 239000012535 impurity Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 10
- 238000002513 implantation Methods 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 56
- 210000000746 body region Anatomy 0.000 description 14
- 239000004642 Polyimide Substances 0.000 description 13
- 229920001721 polyimide Polymers 0.000 description 13
- 238000002955 isolation Methods 0.000 description 6
- 238000007667 floating Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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Abstract
【解決手段】絶縁層30に連通溝40が形成されていない部分では、半導体ウエハ2の表面側に保護テープ60を貼り付けると、表面電極20の表面、及び、絶縁層30の表面に保護テープ60が貼り付く。一方、絶縁層30に連通溝40が形成されている部分では、半導体ウエハ2の表面に保護テープ60を貼り付けると、表面電極20の表面には保護テープ60が貼り付く。連通溝40が形成されているため、絶縁層30の表面には保護テープ60が貼り付かない。そのため、隙間70は、連通溝40を介して、ダイシングライン溝50と連通している。その後、半導体ウエハ2の裏面を加工する際に、半導体ウエハ2を真空環境下に置いたとしても、隙間70内の空気は、連通溝40及びダイシングライン溝50を通って半導体ウエハ2の外周縁から外部に排出される。
【選択図】図4
Description
10:素子領域
12:半導体領域
14:終端領域
20:表面電極
22:信号パッド
30:絶縁層
40:連通溝
50:ダイシングライン溝
60:保護テープ
70:隙間
102:トレンチ
104:ゲート絶縁膜
105:絶縁膜
106:ゲート電極
107:導電体領域
110:コンタクト領域
112:トップボディ領域
114:フローティング領域
116:ボトムボディ領域
118:ドリフト領域
120:層間絶縁膜
122:分離領域
124:終端絶縁膜
Claims (6)
- 半導体ウエハの複数の素子領域のそれぞれに、表面電極と、その表面電極の周縁部に半導体ウエハの表面からの高さが表面電極より高くなる絶縁層とを形成する表面構造形成工程と、
半導体ウエハの表面に、平面視したときに絶縁層を挟んで表面電極の周囲を取り囲んでおり、半導体ウエハの表面からの高さが絶縁層よりも低く、半導体ウエハの外周縁まで伸びるダイシングライン溝を形成するダイシングライン溝形成工程と、
絶縁層に、表面電極側からダイシングライン溝を形成する位置まで伸びる連通溝を形成する連通溝形成工程と、
ダイシングライン溝及び連通溝が形成された半導体ウエハの表面側に保護テープを貼り付ける貼付工程と、
保護テープが貼り付けられた半導体ウエハの裏面を加工する裏面加工工程と、
を備える、ことを特徴とする半導体装置の製造方法。 - 裏面加工工程は、半導体ウエハの裏面に不純物を注入する注入工程を含む、
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 注入工程は、
半導体ウエハの複数の素子領域のそれぞれの裏面の一部に第1導電型の不純物を注入する工程と、
半導体ウエハの複数の素子領域のそれぞれの裏面の他の一部に第2導電型の不純物を注入する工程と、
を含む、ことを特徴とする請求項2に記載の半導体装置の製造方法。 - 裏面加工工程の後、ダイシングライン溝に沿って半導体ウエハをダイシングするダイシング工程をさらに備える、
ことを特徴とする請求項1から3のいずれか一項に記載の半導体装置の製造方法。 - 複数の素子領域を有する半導体ウエハであって、
複数の素子領域のそれぞれは、表面電極と、その表面電極の周縁部に半導体ウエハの表面からの高さが表面電極より高くなる絶縁層とを有しており、
半導体ウエハの表面には、平面視したときに絶縁層を挟んで表面電極の周囲を取り囲んでおり、半導体ウエハの表面からの高さが絶縁層よりも低く、半導体ウエハの外周縁まで伸びるダイシングライン溝が形成されており、
絶縁層には、表面電極側からダイシングライン溝まで伸びる連通溝が形成されている、
ことを特徴とする半導体ウエハ。 - 半導体装置であって、
半導体基板と、
半導体基板の表面に形成された表面電極と、
半導体基板の表面であって表面電極の周縁部に形成され、半導体基板の表面からの高さが表面電極よりも高い絶縁層と、
を有しており、
絶縁層には、表面電極側から半導体装置の外周縁まで伸びる連通溝が形成されている、
ことを特徴とする半導体装置。
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JP2013007129A JP2014138143A (ja) | 2013-01-18 | 2013-01-18 | 半導体装置の製造方法、半導体ウエハ、及び、半導体装置 |
US14/134,325 US9214522B2 (en) | 2013-01-18 | 2013-12-19 | Production method of semiconductor device, semiconductor wafer, and semiconductor device |
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JP2013007129A JP2014138143A (ja) | 2013-01-18 | 2013-01-18 | 半導体装置の製造方法、半導体ウエハ、及び、半導体装置 |
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JP6815237B2 (ja) * | 2017-03-16 | 2021-01-20 | 三菱電機株式会社 | 半導体装置 |
CN110838486B (zh) * | 2018-08-17 | 2023-04-07 | 力智电子股份有限公司 | 功率晶体管元件 |
CN111613529B (zh) * | 2020-05-27 | 2023-05-23 | 华天慧创科技(西安)有限公司 | 一种晶圆的封装工艺 |
CN116913773B (zh) * | 2023-09-12 | 2024-01-26 | 威海市泓淋电力技术股份有限公司 | 一种半导体芯片及其形成方法 |
Citations (7)
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JP2001274129A (ja) * | 2000-03-27 | 2001-10-05 | Nec Kansai Ltd | 半導体ウェーハ及びその製造方法 |
JP2002184777A (ja) * | 2000-12-15 | 2002-06-28 | Toshiba Corp | 半導体装置 |
JP2002222777A (ja) * | 2001-01-29 | 2002-08-09 | Murata Mfg Co Ltd | 半導体装置及びその製造方法 |
JP2006318989A (ja) * | 2005-05-10 | 2006-11-24 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2007036129A (ja) * | 2005-07-29 | 2007-02-08 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2007149974A (ja) * | 2005-11-28 | 2007-06-14 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
JP2007288092A (ja) * | 2006-04-20 | 2007-11-01 | Elpida Memory Inc | 半導体装置及びその製造方法 |
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JP4143488B2 (ja) | 2003-06-30 | 2008-09-03 | Necエンジニアリング株式会社 | テープ貼付装置 |
JP4665429B2 (ja) | 2004-04-26 | 2011-04-06 | 富士電機システムズ株式会社 | 半導体素子の製造方法 |
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JP2001274129A (ja) * | 2000-03-27 | 2001-10-05 | Nec Kansai Ltd | 半導体ウェーハ及びその製造方法 |
JP2002184777A (ja) * | 2000-12-15 | 2002-06-28 | Toshiba Corp | 半導体装置 |
JP2002222777A (ja) * | 2001-01-29 | 2002-08-09 | Murata Mfg Co Ltd | 半導体装置及びその製造方法 |
JP2006318989A (ja) * | 2005-05-10 | 2006-11-24 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2007036129A (ja) * | 2005-07-29 | 2007-02-08 | Renesas Technology Corp | 半導体装置の製造方法 |
JP2007149974A (ja) * | 2005-11-28 | 2007-06-14 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
JP2007288092A (ja) * | 2006-04-20 | 2007-11-01 | Elpida Memory Inc | 半導体装置及びその製造方法 |
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US20140203411A1 (en) | 2014-07-24 |
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