TWI688072B - 半導體積體電路裝置 - Google Patents

半導體積體電路裝置 Download PDF

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TWI688072B
TWI688072B TW105111375A TW105111375A TWI688072B TW I688072 B TWI688072 B TW I688072B TW 105111375 A TW105111375 A TW 105111375A TW 105111375 A TW105111375 A TW 105111375A TW I688072 B TWI688072 B TW I688072B
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insulating film
fuse
interlayer insulating
fuse element
film
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南志昌
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日商艾普凌科有限公司
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Abstract

以為了緩和封裝的應力而塗佈的聚醯亞胺作為遮罩來選擇性地除去所被配置的保險絲(fuse)元件(103)上的BPSG膜及用以層疊金屬配線的金屬間層間絕緣膜，以及設於其上的矽氮化膜，以保險絲切斷容易實施的方式，在保險絲元件的上方設置開口領域(108)。在該開口領域的保險絲元件的中央部的兩側附近取一定的間隔在保險絲元件間設置狹縫(201)，藉此在雷射切斷時容易吹掉絕緣膜，可減低對於保險絲元件之下的元件分離絕緣膜的物理性的損傷，防止與矽基板的導通。

Description

半導體積體電路裝置
本發明是有關具有保險絲元件的半導體積體電路裝置。
在半導體裝置的製造工程中，有晶圓製造工程終了後，例如利用雷射來切斷例如使用多晶矽或金屬的保險絲元件，藉此進行電路構成要素的設定之方法。若利用此方法，則在測定半導體裝置的電氣特性之後，藉由修正電阻的值，可取得所望的特性。因此，在重視類比特性的半導體裝置中成為特別有效的手段。
在圖5、圖6顯示以往的半導體積體電路裝置的一例。圖5是保險絲元件103的平面圖，圖6是沿著圖5的A-A’的剖面圖。如圖5所示般，保險絲元件103是設在元件分離絕緣膜102上，以和MOS電晶體的閘極電極(未圖示)同一的導電材之被摻雜雜質的多結晶Si膜所形成。
並且，在保險絲元件103的上部是設有用以藉由雷射 來切斷保險絲元件103的中心之開口領域108。該開口領域108以往是藉由分別利用遮罩來依序選擇性地蝕刻層間絕緣膜105及矽氮化膜106而設，該層間絕緣膜105是為了金屬層疊化而設，該矽氮化膜106是以保護內部元件從外侵入水分為目的而設。此時，保險絲元件103上的絕緣膜是必須一面考慮在絕緣膜的堆積或蝕刻等製程產生的偏差、切斷時的雷射強度偏差，一面調整成某程度的膜厚的範圍。因為若保險絲元件103露出，則該保險絲元件103會受到水分的影響膨脹，在露出的保險絲元件103與被絕緣膜覆蓋的保險絲元件103的境界產生龜裂，有可能對內部元件帶來不良影響。另一方面，在雷射之保險絲元件103切斷時，需要與保險絲元件103同時吹掉絕緣膜。此時若保險絲元件103上的絕緣膜太過厚，則保險絲元件103上的絕緣膜不易吹掉，吹掉用的熱能量也會傳至保險絲元件103下的元件分離絕緣膜102，在元件分離絕緣膜102產生物理性損傷，導致龜裂的產生。一旦飛散的保險絲元件103的殘留物進入該產生的龜裂，則有可能與矽基板導通，引起電氣特性異常。
作為上述課題的對策，測定開口部的膜厚，嚴格管理，或將保險絲元件103下的絕緣膜形成比其他的元件分離膜厚更厚，或在底層鋪上損傷阻止材等，為了緩和對底層的損傷，而下各種的工夫(例如參照專利文獻1)。
[先行技術文獻] [專利文獻]
[專利文獻1]日本特開2010-056557號公報
然而，若將保險絲元件103下的絕緣膜102形成比其他的元件分離膜的厚度更厚，或在底層鋪上用以阻止損傷的材料，則會擔憂矽基板101與元件分離絕緣膜102的階差更嚴峻。因此被形成於矽基板101上的元件的接觸的寬高比(aspect ratio)會變成非常高，有可能未形成接觸、或雖導通但顯示異常高的接觸電阻值。相反的，即使被形成於基板101上的元件的接觸導通，也有可能對保險絲元件103的接觸貫通保險絲元件103的膜產生品質異常。
本發明是以提供一種不會有使上述那樣的擔憂發生的情形，且在保險絲切斷時不使品質異常發生可安定地切斷保險絲的半導體積體電路裝置為目的。
本發明為了解決上述課題，而使用以下那樣的手段。
首先，設為一種半導體積體電路裝置，其特徵係由下列所成：半導體基板；元件分離絕緣膜，其係設於前述半導體基板的表面；複數的保險絲元件，其係於前述元件分離絕緣膜上取 間隔來配置，由多結晶矽所構成；絕緣膜，其係配置於前述保險絲元件上；層間絕緣膜，其係設於前述絕緣膜上；矽氮化膜，其係設於前述層間絕緣膜上；開口領域，其係除去前述矽氮化膜及前述層間絕緣膜的一部分，設在前述保險絲元件的上方；及凹部，其係除去前述開口領域下的前述層間絕緣膜的剩餘部分，在前述保險絲元件的保險絲中央部的兩側附近取一定的間隔來配置。
又，在前述保險絲元件的保險絲中央部的兩側附近取一定的間隔來配置的凹部為狹縫狀。
又，在前述保險絲元件的保險絲中央部的兩側附近取一定的間隔來配置的凹部為點狀。
又，在前述保險絲元件的保險絲中央部的兩側附近取一定的間隔來配置的凹部在鄰接的保險絲元件間為一個。
若根據本發明，則即使加厚設定保險絲元件上的絕緣膜，還是可藉由在保險絲元件中央部的兩側附近取一定的間隔來配置狹縫狀的凹部，在雷射切斷時容易將絕緣膜吹掉，減低對於保險絲元件下的元件分離絕緣膜的物理性的損傷，防止與半導體基板的導通。
101‧‧‧矽半導體基板
102‧‧‧元件分離絕緣膜
103‧‧‧保險絲元件
104‧‧‧絕緣膜(BPSG膜)
105‧‧‧金屬配線間的層間絕緣膜
106‧‧‧矽氮化膜
107‧‧‧聚醯亞胺
108‧‧‧開口領域
201‧‧‧凹部
圖1是本發明的第一實施例的半導體積體電路裝置的模式平面圖。
圖2是沿著圖1的半導體積體電路裝置的A-A’的模式剖面圖。
圖3是本發明的第二實施例的半導體積體電路裝置的模式平面圖。
圖4是本發明的第三實施例的半導體積體電路裝置的模式平面圖。
圖5是以往的半導體積體電路裝置的模式平面圖。
圖6是沿著圖5的以往的半導體積體電路裝置的A-A’的模式剖面圖。
以下，根據圖面說明此發明的實施形態。
圖1是成為本發明的第一實施例的半導體積體電路裝置的模式平面圖，圖2是沿著本發明的第一實施例的半導體積體電路裝置的圖1的A-A’的模式剖面圖。首先，利用圖1來說明有關保險絲領域的平面構造。在矽半導體基板上所設的元件分離絕緣膜的表面配置有複數個保險絲元件103。保險絲元件103的保險絲中央部是比兩端部細，而使能夠容易藉由雷射來切斷。然後，在保險絲元件103的保險絲中央部的兩側附近取一定的間隔來配置狹縫狀的凹部201。而且，在複數的保險絲元件103的中央部的上方，為了進行雷射的切斷，而配置有藉由蝕刻來去除聚醯 亞胺107、作為保護膜的矽氮化膜106、然後層間絕緣膜105至途中的開口領域108(參照圖2)。因此，凹部201是形成露出於開口領域108的底。在此，本發明的特徵是與保險絲元件103鄰接，在保險絲元件103上的層間絕緣膜105配置狹縫狀的凹部201的點。在本實施例中，狹縫狀的凹部201是平面視成為矩形。
圖2是沿著圖1的A-A’的半導體裝置的模式剖面圖。在矽半導體基板101上，元件分離絕緣膜102例如設為4000~7000Å程度，在元件分離絕緣膜102上，保險絲元件103是以和MOS電晶體的閘極電極(未圖示)同一層同一導電材之被摻雜雜質的多結晶Si膜所形成。其厚度是2000~4000Å程度。在保險絲元件103上，設有用以將被形成於矽基板上的元件與金屬配線絕緣的絕緣膜，例如BPSG膜104，且在其上設有為了金屬配線與金屬配線的層疊化的層間絕緣膜105。並且，以保護內部元件從外侵入水分為目的，層疊有矽氮化膜106。然後，最後層疊封裝的應力緩和用的聚醯亞胺107之後，在聚醯亞胺107設置開口領域108，其次以剩下的聚醯亞胺107本身作為遮罩，繼續蝕刻矽氮化膜106及層間絕緣膜105的一部分，藉此設置開口領域108。其次，利用別的遮罩來圖案化，將層間絕緣膜105的剩餘部分蝕刻，藉此設置狹縫狀的凹部201。此時，層間絕緣膜105與下層的絕緣膜104因為蝕刻的選擇比小，所以在兩者的界面停止蝕刻困難，亦可將絕緣膜104蝕刻少許。
藉由設為如此的構造，即使加厚保險絲元件上的層間絕緣膜，還是會因為在保險絲元件的兩側有狹縫狀的凹部201，所以層間絕緣膜105會沿著保險絲元件來分離，在雷射照射時容易將層間絕緣膜105吹掉。因此，即使保險絲元件上的層間絕緣膜變厚，也不必擴大雷射的輸出，可減低對於保險絲元件103下的元件分離絕緣膜102的物理性的損傷。在本實施例中，凹部是平面視為矩形的狹縫，但當然凹部是亦可為多角形或橢圓形狀。
圖3是本發明的第二實施例的半導體積體電路裝置的模式平面圖。在第一實施例中，凹部201為長方形的狹縫，相對的，在此是設為複數的正方形的點(dot)形狀的凹部201。由於在保險絲元件的兩側有複數的正方形的凹部201，因此層間絕緣膜105是沿著保險絲元件來部分地被分離，雷射照射時容易將層間絕緣膜105吹掉。另外，點形狀是可為矩形，或圓形也無妨。
圖4是本發明的第三實施例的半導體積體電路裝置的模式平面圖。在圖1及圖3中，在相鄰的保險絲元件之間配置有2列的凹部201，但如圖4所示般，即使是在相鄰的保險絲元件之間配列1列的凹部201的構成也無妨。此情況，可擴大凹部的寬度(相鄰的保險絲元件的間隔方向的寬度)，保險絲切斷變更容易，且當層間絕緣膜105藉由雷射照射而被吹掉時，具有對於被吹掉時相鄰的保險絲元件的下方的元件分離絕緣膜102造成損傷的可能性更低的優點。
在上述說明中，是顯示以第1遮罩來持續蝕刻聚醯亞胺、矽氮化膜及層間絕緣膜的一部分而形成開口領域，其次，以第2遮罩來蝕刻層間絕緣膜的剩餘部分，藉此設置凹部的工程，但亦可為以第1遮罩來持續蝕刻聚醯亞胺、矽氮化膜而形成開口領域，其次，以第2遮罩來蝕刻層間絕緣膜，藉此設置凹部的工程。如本發明般藉由設置凹部，容易吹掉層間絕緣膜，因此可為如此的工程設定。並且，聚醯亞胺是亦有不使用的情形，但該情況當然完全同樣本發明可適用。
如以上般，在保險絲元件的保險絲中央部的兩側附近取一定的間隔在層間絕緣膜配置凹部，藉此即使加厚設定保險絲元件上的絕緣膜，還是可在雷射切斷時容易將絕緣膜吹掉，減低對於保險絲元件下的元件分離絕緣膜的物理性的損傷，防止與矽基板的導通。
103‧‧‧保險絲元件
108‧‧‧開口領域
201‧‧‧凹部

Claims (3)

  1. 一種半導體積體電路裝置，其特徵係由下列所成：半導體基板；元件分離絕緣膜，其係設於前述半導體基板的表面；複數的保險絲元件，其係於前述元件分離絕緣膜上取間隔來配置，由多結晶矽所構成；絕緣膜，其係配置於前述保險絲元件上；層間絕緣膜，其係設於前述絕緣膜上；矽氮化膜，其係設於前述層間絕緣膜上；開口領域，其係設於前述保險絲元件的上方，前述矽氮化膜及前述層間絕緣膜的一部分被除去；及狹縫狀的凹部，其係設於前述開口領域下的前述層間絕緣膜的剩餘部分，在前述保險絲元件的保險絲中央部的兩側取一定的間隔來配置。
  2. 一種半導體積體電路裝置，其特徵係由下列所成：半導體基板；元件分離絕緣膜，其係設於前述半導體基板的表面；複數的保險絲元件，其係於前述元件分離絕緣膜上取間隔來配置，由多結晶矽所構成；絕緣膜，其係配置於前述保險絲元件上；層間絕緣膜，其係設於前述絕緣膜上；矽氮化膜，其係設於前述層間絕緣膜上；開口領域，其係設於前述保險絲元件的上方，前述矽氮化膜及前述層間絕緣膜的一部分被除去；及 複數的點形狀的凹部，其係設於前述開口領域下的前述層間絕緣膜的剩餘部分，在前述保險絲元件的保險絲中央部的兩側，分別取一定的間隔，配置於與鄰接的保險絲元件之間。
  3. 一種半導體積體電路裝置，其特徵係由下列所成：半導體基板；元件分離絕緣膜，其係設於前述半導體基板的表面；複數的保險絲元件，其係於前述元件分離絕緣膜上取間隔來配置，由多結晶矽所構成；絕緣膜，其係配置於前述保險絲元件上；層間絕緣膜，其係設於前述絕緣膜上；矽氮化膜，其係設於前述層間絕緣膜上；開口領域，其係設於前述保險絲元件的上方，前述矽氮化膜及前述層間絕緣膜的一部分被除去；及凹部，其係設於前述開口領域下的前述層間絕緣膜的剩餘部分，在前述保險絲元件的保險絲中央部的兩側取一定的間隔來配置，前述凹部在鄰接的保險絲元件間為一個。
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