CN106098685A - 半导体集成电路装置 - Google Patents

半导体集成电路装置 Download PDF

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CN106098685A
CN106098685A CN201610276143.4A CN201610276143A CN106098685A CN 106098685 A CN106098685 A CN 106098685A CN 201610276143 A CN201610276143 A CN 201610276143A CN 106098685 A CN106098685 A CN 106098685A
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南志昌
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Seiko Instruments Inc
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Abstract

本发明题为半导体集成电路装置。将为封装件的应力缓和而涂敷的聚酰亚胺作为掩模选择性除去用于层叠所配置的熔丝元件（103）上的BPSG膜和金属布线的金属间层间绝缘膜、和再在其上设置的氮化硅膜，从而在熔丝元件的上方设置开口区域（108），以能够容易实施熔丝切断。在该开口区域的熔丝元件的中央部的两侧附近隔着一定间隔，在熔丝元件间设置狭缝（201），从而在激光切断时会容易吹走绝缘膜，并降低对处于熔丝元件下的元件分离绝缘膜的物理伤害，能够防止与硅衬底的导通。

Description

半导体集成电路装置
技术领域
本发明涉及具有熔丝元件的半导体集成电路装置。
背景技术
在半导体装置的制造工序中，有这样的方法，即，在结束晶片制造工序之后，例如利用激光，切断例如利用多晶硅或金属的熔丝元件来进行电路构成要素的设定的方法。若用该方法，则在测定半导体装置的电特性后，能够通过修正电阻的值而得到期望的特性。因此在重视模拟特性的半导体装置中成为特别有效的手段。
在图5、图6示出现有的半导体集成电路装置的一个例子。图5是熔丝元件103的平面图，图6是沿着图5的A－A’的截面图。如图5所示，熔丝元件103设在元件分离绝缘膜102上，由与MOS晶体管的栅电极（未图示）相同的导电材料的、掺杂杂质的多晶硅膜形成。
另外，在熔丝元件103的上部设有用于以激光切断熔丝元件103的中心的开口区域108。该开口区域108一直以来通过将为金属层叠化而设置的层间绝缘膜105和以保护内部元件免受来自外来的水分侵入为目的而设置的氮化硅膜（シリコン窒化膜）106分别用作为掩模依次进行选择性蚀刻而设置。此时，熔丝元件103上的绝缘膜需要先考虑绝缘膜的沉积、蚀刻等工艺中产生的偏差、切断时的激光强度偏差，并且调整到一定程度的膜厚范围。原因是，若熔丝元件103露出，则有可能该熔丝元件103受到水分的影响而膨胀，裂缝会进入到露出的熔丝元件103和被绝缘膜覆盖的熔丝元件103的边界，从而对内部元件带来负面影响。另一方面，在利用激光进行熔丝元件103切断时，需要与熔丝元件103同时吹走绝缘膜。此时若熔丝元件103上的绝缘膜太厚，则熔丝元件103上的绝缘膜轻易不会吹走，用于吹走的热能量还会传递到熔丝元件103下的元件分离绝缘膜102，对元件分离绝缘膜102造成物理伤害，从而导致产生裂缝。若飞散的熔丝元件103的残留物进入该产生的裂缝，则有可能与硅衬底导通，从而在电特性引起异常。
作为上述课题的对策，想出了测定开口部的膜厚并严格进行管理，或者使熔丝元件103下的绝缘膜厚于其他元件分离膜厚，或者向基底铺上伤害格挡材料等用于缓和对基底的伤害的各种办法（例如，参照专利文献1）。
现有技术文献
专利文献
专利文献1：日本特开2010－056557号公报。
发明内容
发明要解决的课题
然而，如果使熔丝元件103下的绝缘膜102厚于其他元件分离膜的厚度，或者对基底铺上用于格挡伤害的材料，就要担心硅衬底101与元件分离绝缘膜102的阶梯差会更加严重。因此形成在硅衬底101上的元件的接触部的长宽比会变得非常高，从而有可能不会形成接触部，或者虽然导通但显示异常高的接触部电阻值。相反，即便形成在硅衬底101上的元件的接触部导通，也有可能对熔丝元件103的接触部贯通熔丝元件103的膜从而产生质量异常。
本发明目的在于提供不会出现如上所述的担心，且熔丝切断时不会出现质量异常而能够稳定地切断熔丝的半导体集成电路装置。
用于解决课题的方案
本发明为了解决上述课题，采用如以下的方案。
首先，一种半导体集成电路装置，其特征在于包括：
半导体衬底；
元件分离绝缘膜，设在所述半导体衬底的表面；
由第1多晶硅构成的多个熔丝元件，在所述元件分离绝缘膜之上隔开间隔而配置；
绝缘膜，配置在所述熔丝元件上；
层间绝缘膜，设在所述绝缘膜上；
氮化硅膜，设在所述层间绝缘膜上；
开口区域，除去所述氮化硅膜及所述层间绝缘膜的一部分而设在所述熔丝元件的上方；以及
凹部，除去所述开口区域下的所述层间绝缘膜的残余部，在所述熔丝元件的熔丝中央部的两侧附近隔着一定间隔而配置。
另外，半导体集成电路装置的特征在于：在所述熔丝元件的熔丝中央部的两侧附近隔着一定间隔而配置的凹部为狭缝状。
另外，半导体集成电路装置的特征在于：在所述熔丝元件的熔丝中央部的两侧附近隔着一定间隔而配置的凹部为点状。
另外，半导体集成电路装置的特征在于：在所述熔丝元件的熔丝中央部的两侧附近隔着一定间隔而配置的凹部在邻接的熔丝元件间有一个。
发明效果
依据本发明，即使将熔丝元件上的绝缘膜设定为较厚，也能通过在熔丝元件中央部的两侧附近隔着一定间隔而配置狭缝状的凹部，在激光切断时容易吹走绝缘膜，并降低对熔丝元件下的元件分离绝缘膜的物理伤害，从而防止与半导体衬底的导通。
附图说明
图1是本发明的第一实施例的半导体集成电路装置的示意平面图。
图2是沿着图1的半导体集成电路装置的A－A’的示意截面图。
图3是本发明的第二实施例的半导体集成电路装置的示意平面图。
图4是本发明的第三实施例的半导体集成电路装置的示意平面图。
图5是现有的半导体集成电路装置的示意平面图。
图6是沿着图5的现有的半导体集成电路装置的A－A’的示意截面图。
具体实施方式
以下，基于附图，对本发明的实施方式进行说明。
图1是成为本发明的第一实施例的半导体集成电路装置的示意平面图，图2是沿着本明的第一实施例的半导体集成电路装置的图1中的A－A’的示意截面图。首先，利用图1，对熔丝区域的平面构造进行说明。设在硅半导体衬底上的元件分离绝缘膜的表面配置有多个熔丝元件103。熔丝元件103的熔丝中央部成为比两端部细，以用激光容易切断。而且，在熔丝元件103的熔丝中央部的两侧附近隔着一定间隔配置有狭缝状的凹部201。进而，为进行利用激光的切断，在多个熔丝元件103的中央部的上方，配置有聚酰亚胺107、作为保护膜的氮化硅膜106、以及层间绝缘膜105因蚀刻而消除至中途的开口区域108（参照图2）。因此，凹部201会露出到开口区域108的底部而形成。在此，本发明的特征在于与熔丝元件103邻接而在熔丝元件103上的层间绝缘膜105配置狭缝状的凹部201这一点。在本实施例中狭缝状的凹部201俯视为矩形。
图2是沿着图1的A－A’的半导体装置的示意截面图。元件分离绝缘膜102在硅半导体衬底101上例如以4000～7000Å左右设置，在元件分离绝缘膜102上熔丝元件103在与MOS晶体管的栅电极（未图示）同一层由掺杂相同的导电材料的杂质的多晶硅膜形成。它的厚度为2000～4000Å左右。在熔丝元件103上，设有用于对形成在硅衬底上的元件和金属布线进行绝缘的绝缘膜例如BPSG膜104，其上设有金属布线和用于金属布线的层叠化的层间绝缘膜105。另外，为了保护内部元件免受来自外来的水分侵入的目的而层叠氮化硅膜106。而且最后层叠用于封装件的应力缓和的聚酰亚胺107后，在聚酰亚胺107设置开口区域108，接着以剩下的聚酰亚胺107自身为掩模，连续蚀刻氮化硅膜106及层间绝缘膜105的一部分，从而设置开口区域108。接着，利用其他掩模进行构图，蚀刻层间绝缘膜105的剩下部分，从而设置狭缝状的凹部201。此时，层间绝缘膜105和下层的绝缘膜104因蚀刻的选择比小而难以在两者的界面停止蚀刻，即使将绝缘膜104蚀刻一些也可。
通过这样的构造，即便加厚熔丝元件上的层间绝缘膜，也因熔丝元件的两侧存在狭缝状的凹部201而层间绝缘膜105沿着熔丝元件分离，在激光照射时会容易吹走层间绝缘膜105。因此，即便熔丝元件上的层间绝缘膜变厚也无需增大激光的输出，能够降低对熔丝元件103下的元件分离绝缘膜102的物理伤害。本实施例中，设凹部为俯视矩形的狭缝，但是凹部显然也可为多边形或者椭圆形状。
图3是本发明的第二实施例的半导体集成电路装置的示意平面图。第一实施例中凹部201为长方形的狭缝，而在此设为多个正方形的点形状的凹部201。在熔丝元件的两侧有多个正方形的凹部201，因此层间绝缘膜105沿着熔丝元件局部分离，从而在激光照射时会容易吹走层间绝缘膜105。此外，点形状也可为矩形，圆形也无妨。
图4是本发明的第三实施例的半导体集成电路装置的示意平面图。在图1及图3中，在相邻的熔丝元件之间配置有2列的凹部201，但是如图4所示，以在相邻的熔丝元件之间配置1列的凹部201的方式构成也无妨。在该情况下，具有这样的优点：可以增大凹部的宽度（相邻的熔丝元件的间隔方向的宽度），不仅更加容易进行熔丝切断，而且进一步降低当层间绝缘膜105因激光照射而吹走时对相邻的熔丝元件的下方的元件分离绝缘膜102造成伤害的可能性。
上述说明中，示出以第1掩模连续蚀刻聚酰亚胺、氮化硅膜及层间绝缘膜的一部分而形成开口区域，接着，以第2掩模蚀刻层间绝缘膜的剩余部分，从而设置凹部这一工序，但是也可为这样的工序，即，以第1掩模连续蚀刻聚酰亚胺、氮化硅膜而形成开口区域，接着，以第2掩模蚀刻层间绝缘膜而设置凹部。如本发明那样通过设置凹部会容易吹走层间绝缘膜，因此能够设定这样的工序。另外，也有不使用聚酰亚胺的情况，但是在该情况下显然也能完全同样适用本发明。
如以上那样，通过在熔丝元件的熔丝中央部的两侧附近隔着一定间隔而在层间绝缘膜配置凹部，即便将熔丝元件上的绝缘膜设定为较厚，也会在激光切断时容易吹走绝缘膜，降低对熔丝元件下的元件分离绝缘膜的物理伤害，从而能够防止与硅衬底的导通。
标号说明
101　硅半导体衬底；102　元件分离绝缘膜；103　熔丝元件；104　绝缘膜（BPSG膜）；105　金属布线间的层间绝缘膜；106　氮化硅膜；107　聚酰亚胺；108　开口区域；201　凹部。

Claims (4)

1.一种半导体集成电路装置，其中包括：
半导体衬底；
元件分离绝缘膜，设在所述半导体衬底的表面；
由多晶硅构成的多个熔丝元件，在所述元件分离绝缘膜之上隔开间隔而配置；
绝缘膜，配置在所述熔丝元件上；
层间绝缘膜，设在所述绝缘膜上；
氮化硅膜，设在所述层间绝缘膜上；
开口区域，设在所述熔丝元件的上方，除去了所述氮化硅膜及所述层间绝缘膜的一部分；以及
凹部，设在所述开口区域下的所述层间绝缘膜的残余部，并在所述熔丝元件的熔丝中央部的两侧隔着一定间隔而配置。
2.如权利要求1所述的半导体集成电路装置，其中，在所述熔丝中央部的两侧隔着一定间隔而配置的凹部为狭缝状。
3.如权利要求1所述的半导体集成电路装置，其中，在所述熔丝中央部的两侧隔着一定间隔而配置的凹部为点形状。
4.如权利要求1至3中的任一项所述的半导体集成电路装置，其中，在所述熔丝中央部的两侧隔着一定间隔而配置的凹部在邻接的熔丝元件间为一个。
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