US20140175601A1 - Anti-fuse structure and anti-fuse programming method - Google Patents
Anti-fuse structure and anti-fuse programming method Download PDFInfo
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- US20140175601A1 US20140175601A1 US13/726,242 US201213726242A US2014175601A1 US 20140175601 A1 US20140175601 A1 US 20140175601A1 US 201213726242 A US201213726242 A US 201213726242A US 2014175601 A1 US2014175601 A1 US 2014175601A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the invention relates to an anti-fuse structure and an anti-fuse programming method, and more particularly, to an anti-fuse structure and an anti-fuse programming method having a predictable rupture point.
- PROM Programmable read-only memory
- FPROM field programmable read-only memory
- OTP NUM one-time programmable non-volatile memory
- the anti-fuse structure which performs the opposite function to a fuse structure, is permanently programmed by providing a current exceeding a specified limit to “blow” the anti-fuse structure.
- an anti-fuse structure consist of a transistor is programmed when the gate dielectric breakdown occurs. In other words, a rupture point in a location on the gate dielectric layer that shorts a word line to a bit line is always expected when programming the anti-fuse structure.
- an anti-fuse structure includes a substrate having at least a shallow trench isolation (STI) formed therein, a notch formed between the substrate and the STI, an electrode structure formed on the substrate, the electrode structure filling the notch, and a doped region formed in the substrate on a side of the electrode structure opposite to the notch.
- STI shallow trench isolation
- an anti-fuse structure includes a substrate having at least an insulating structure formed therein, a conductive layer formed on the substrate, the conductive layer comprising at least a first part covering a portion of the substrate and a portion of the insulating structure, and a doped region formed in the substrate on a side of the conductive layer opposite to the insulating structure.
- an anti-fuse programming method is further provided.
- the anti-fuse structure programming method first provides an anti-fuse structure.
- the anti-fuse structure includes a substrate having at least a STI formed therein, a notch formed between the substrate and the STI, an electrode structure formed on the substrate, the electrode structure filling the notch, and a doped region formed in the substrate on a side of the electrode structure opposite to the notch.
- a programming voltage is provided to the anti-fuse structure and a rupture point located at the notch is formed according to the anti-fuse structure programming method.
- the rupture point is located at the notch or at the bird's beak as expected.
- the rupture point of the anti-fuse structure is predictably limited.
- FIGS. 1-2 are schematic drawings illustrating an anti-fuse structure provided by a first preferred embodiment of the present invention
- FIG. 2 is a schematic drawing in a step subsequent to FIG. 1 .
- FIG. 3 is a schematic drawing illustrating an anti-fuse programming method provided by the first preferred embodiment of the present invention.
- FIGS. 4-5 are schematic drawings illustrating an anti-fuse structure provided by a second preferred embodiment of the present invention
- FIG. 5 is a schematic drawing in a step subsequent to FIG. 4 .
- FIG. 6 is a schematic drawing illustrating an anti-fuse programming method provided by the second preferred embodiment of the present invention.
- FIGS. 1-3 wherein FIGS. 1-2 are schematic drawings illustrating an anti-fuse structure provided by a first preferred embodiment of the present invention and FIG. 3 is a schematic drawing illustrating an anti-fuse programming method provided by the first preferred embodiment of the present invention.
- the preferred embodiment first provides a substrate 102 .
- the substrate 102 can be a conventional semiconductor substrate, such as a bulk silicon substrate or an epitaxial silicon substrate, but not limited to this.
- At least an insulating structure such as a shallow trench isolation (STI) 110 is provided in the substrate 102 .
- STI shallow trench isolation
- the STI 110 is formed by the following steps: a patterned hard mask (not shown) including at least a pad oxide layer and a silicon nitride layer is formed on the substrate 102 . Then, a suitable etching process is performed to etch the substrate 102 through the patterned hard mask to form a recess (not shown) in the substrate 102 and followed by filling the recess with an insulating material. Subsequently, the superfluous insulating material and the patterned hard mask are removed, thus the STI 110 is obtained as shown in FIG. 1 . It is well-known that a notch 112 between the substrate 102 and the STI 110 as shown in FIG. 1 is always formed after removing the pattern hard mask.
- the anti-fuse structure 100 provided by the preferred embodiment includes an electrode structure 120 formed on the substrate 102 and a doped region 130 formed in the substrate 102 on a side of the electrode structure 120 opposite to the notch 110 . Also, the anti-fuse structure 100 includes a lightly-doped drain (LDD) 132 . In the preferred embodiment, the anti-fuse structure 100 is assumed to be a structure of n-type conductivity, therefore the doped region 130 and the LDD 132 include n-type dopants.
- LDD lightly-doped drain
- the anti-fuse structure 100 can be formed as a structure of p-type conductivity in accordance with different requirement, and thus the doped region 130 and the LDD 132 may include p-type dopant.
- the electrode structure 120 which serves as a word line, is electrically connected to a word line contact 140 and the doped region 130 is electrically connected to a bit line through a bit line contact 142 . It is noteworthy that according to the preferred embodiment, the anti-fuse structure 100 always includes only one doped region 130 plus its LDD 132 for providing electrical connection between the word line and the bit line.
- the electrode structure 120 includes a conductive layer 122 and an insulating layer 124 sandwiched between the conductive layer 122 and the substrate 102 .
- the conductive layer 122 includes polysilicon in the preferred embodiment, but not limited to this.
- the conductive layer 122 can be formed of other conductive materials such as metal. In other words, metal gate approach can be adopted in the preferred embodiment.
- the insulating layer 124 includes exemplarily a silicon oxide layer in the preferred embodiment, however the insulating layer 124 can include any suitable dielectric material. As shown in FIG. 2 , the insulating layer 124 extends into the notch 112 . More important, the insulating layer 124 includes a non-uniform thickness according to the preferred embodiment.
- the conductive layer 122 includes a first part 122 a covering a portion of the substrate 102 and a portion of the STI 110 . More important, the conductive layer 122 includes a second part 122 b extended from the first part 122 a and filling up the notch 112 as shown in FIG. 2 . In other words, the second part 122 b is formed in between the STI 110 and the substrate 102 .
- FIG. 3 Please refer to FIG. 3 .
- a programming voltage is provided and applied to the anti-fuse structure 100 , thus a channel region 114 is formed as shown FIG. 3 .
- the second part 122 b that is the notch 112 filled by the electrode structure 120 , is the most vulnerable part of the electrode structure 120 because electrical fields concentrate at the sharp profile. Since the second part 122 b obtains the highest electrical fields, a rupture point 126 of the insulating layer 124 is formed at the second part 122 b, that is formed at the notch 112 , when a programming voltage is applied. Consequently, the anti-fuse 100 is blown and programmed.
- the second part 122 b of the electrode structure 120 is formed to fill the notch 112 and thus the electrical fields concentrate at the second part 122 b due the sharp profile of the notch 112 . Accordingly, the rupture point 126 of the insulating layer 124 is easily limited and located at the second part 122 b /the notch 112 during programming. Therefore, the anti-fuse structure 100 provided by the preferred embodiment has an advantage that the rupture point 126 of the insulating layer 124 is always predictably located at the second part 122 b /the notch 112 as expected. Additionally, compared with the conventional insulating layer having constant thickness, the insulating layer 124 provided by the preferred embodiment can be formed to have a variable thickness and thus the manufacturing process is simplified.
- FIGS. 4-6 are schematic drawings illustrating an anti-fuse structure provided by a second preferred embodiment of the present invention and FIG. 6 is a schematic drawing illustrating an anti-fuse programming method provided by the second preferred embodiment of the present invention.
- the preferred embodiment first provides a substrate 202 , and the substrate 202 includes an insulating structure such as field oxide (FOX) structure 210 thereon.
- the FOX structure 210 is formed by performing a thermal oxidation to the substrate 202 and therefore at least a bird's beak portion 212 is always formed at the edge of the FOX structure 210 as shown in FIG. 4 .
- the anti-fuse structure 200 provided by the preferred embodiment includes an electrode structure 220 formed on the substrate 202 and a doped region 230 formed in the substrate 202 on a side of the electrode structure 220 opposite to the FOX structure 210 . Also, the anti-fuse structure 200 includes a LDD 232 .
- the electrode structure 220 which serves as a word line, is electrically connected to a word line contact 240 and the doped region 230 is electrically connected to a bit line through a bit line contact 242 . It is noteworthy that according to the preferred embodiment, the anti-fuse structure 200 always includes only one doped region 230 plus its LDD 232 for providing electrical connection between the word line and the bit line.
- the electrode structure 220 includes a conductive layer 222 and an insulating layer 224 sandwiched between the conductive layer 222 and the substrate 202 . As shown in FIG. 5 , the electrode structure 220 covers a portion of the substrate 202 and a portion of the FOX structure 210 . It is noteworthy that, since a top surface of the FOX structure 210 is higher than a surface of the substrate 202 , the electrode structure 220 includes a lower part 222 a located on the substrate 202 and a higher part 222 b located on and raised by the FOX structure 210 .
- FIG. 6 Please refer to FIG. 6 .
- a programming voltage is provided and applied to the anti-fuse structure 200 , thus a channel region 214 is formed as shown FIG. 6 .
- an adjoining boundary between the lower part 222 a and the higher part 222 b is the most vulnerable part of the electrode structure 220 because electrical fields concentrate at this twisting configuration. Since the adjoining boundary obtains the highest electrical fields, a rupture point 226 of the insulating layer 224 is formed at the adjoining boundary between the lower part 222 a and the higher part 222 b, when a programming voltage is applied. Consequently, the anti-fuse 200 is blown and programmed.
- the adjoining boundary is formed corresponding to the bird's beak 212 of the FOX structure 210 , therefore it is also taken that the rupture point 226 of the insulating layer 224 is formed at the bird's beak 212 .
- the electrical fields concentrate at the bird's beak 212 /the adjoining boundary of the lower part 222 a and the higher part 222 b due to this twisting configuration. Accordingly, the rupture point 226 of the insulating layer 224 is easily limited and located at this adjoining boundary/the bird's beak 212 during programming. Therefore, the anti-fuse structure 200 provided by the preferred embodiment has an advantage that the rupture point 226 of the insulating layer 224 is always predictably located at the bird's beak 212 /the adjoining boundary of the lower part 222 a and the higher part 222 b. Additionally, compared with the conventional insulating layer having constant thickness, the insulating layer 224 provided by the preferred embodiment can be formed to have a variable thickness and thus the manufacturing process is simplified.
- the rupture point of the insulating layer is located at the notch or at the bird's beak as expected.
- the rupture point of the anti-fuse structure is predictably limited.
- the insulating layer provided by the preferred embodiment can be formed to have a variable thickness and thus the manufacturing process is simplified.
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Abstract
Description
- 1. Field of the Invention
- The invention relates to an anti-fuse structure and an anti-fuse programming method, and more particularly, to an anti-fuse structure and an anti-fuse programming method having a predictable rupture point.
- 2. Description of the Prior Art
- Programmable read-only memory (PROM), field programmable read-only memory (FPROM), and one-time programmable non-volatile memory (OTP NUM) are forms of digital memory where the setting of each bit is locked by a fuse or an anti-fuse structure.
- As one type of the one-time programmable memory element, the anti-fuse structure, which performs the opposite function to a fuse structure, is permanently programmed by providing a current exceeding a specified limit to “blow” the anti-fuse structure. For example, an anti-fuse structure consist of a transistor is programmed when the gate dielectric breakdown occurs. In other words, a rupture point in a location on the gate dielectric layer that shorts a word line to a bit line is always expected when programming the anti-fuse structure.
- According to the claimed invention, an anti-fuse structure is provided. The anti-fuse structure includes a substrate having at least a shallow trench isolation (STI) formed therein, a notch formed between the substrate and the STI, an electrode structure formed on the substrate, the electrode structure filling the notch, and a doped region formed in the substrate on a side of the electrode structure opposite to the notch.
- According to the claimed invention, an anti-fuse structure is provided. The anti-fuse structure includes a substrate having at least an insulating structure formed therein, a conductive layer formed on the substrate, the conductive layer comprising at least a first part covering a portion of the substrate and a portion of the insulating structure, and a doped region formed in the substrate on a side of the conductive layer opposite to the insulating structure.
- According to the claimed invention, an anti-fuse programming method is further provided. The anti-fuse structure programming method first provides an anti-fuse structure. The anti-fuse structure includes a substrate having at least a STI formed therein, a notch formed between the substrate and the STI, an electrode structure formed on the substrate, the electrode structure filling the notch, and a doped region formed in the substrate on a side of the electrode structure opposite to the notch. Then, a programming voltage is provided to the anti-fuse structure and a rupture point located at the notch is formed according to the anti-fuse structure programming method.
- According to the anti-fuse structure and anti-fuse programming method, the rupture point is located at the notch or at the bird's beak as expected. In other words, the rupture point of the anti-fuse structure is predictably limited.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIGS. 1-2 are schematic drawings illustrating an anti-fuse structure provided by a first preferred embodiment of the present invention, andFIG. 2 is a schematic drawing in a step subsequent toFIG. 1 . -
FIG. 3 is a schematic drawing illustrating an anti-fuse programming method provided by the first preferred embodiment of the present invention. -
FIGS. 4-5 are schematic drawings illustrating an anti-fuse structure provided by a second preferred embodiment of the present invention, andFIG. 5 is a schematic drawing in a step subsequent toFIG. 4 . -
FIG. 6 is a schematic drawing illustrating an anti-fuse programming method provided by the second preferred embodiment of the present invention. - Please refer to
FIGS. 1-3 , whereinFIGS. 1-2 are schematic drawings illustrating an anti-fuse structure provided by a first preferred embodiment of the present invention andFIG. 3 is a schematic drawing illustrating an anti-fuse programming method provided by the first preferred embodiment of the present invention. As shown inFIG. 1 , the preferred embodiment first provides asubstrate 102. Thesubstrate 102 can be a conventional semiconductor substrate, such as a bulk silicon substrate or an epitaxial silicon substrate, but not limited to this. At least an insulating structure such as a shallow trench isolation (STI) 110 is provided in thesubstrate 102. The STI 110 is formed by the following steps: a patterned hard mask (not shown) including at least a pad oxide layer and a silicon nitride layer is formed on thesubstrate 102. Then, a suitable etching process is performed to etch thesubstrate 102 through the patterned hard mask to form a recess (not shown) in thesubstrate 102 and followed by filling the recess with an insulating material. Subsequently, the superfluous insulating material and the patterned hard mask are removed, thus theSTI 110 is obtained as shown inFIG. 1 . It is well-known that anotch 112 between thesubstrate 102 and the STI 110 as shown inFIG. 1 is always formed after removing the pattern hard mask. - Please refer to
FIG. 2 . Theanti-fuse structure 100 provided by the preferred embodiment includes anelectrode structure 120 formed on thesubstrate 102 and adoped region 130 formed in thesubstrate 102 on a side of theelectrode structure 120 opposite to thenotch 110. Also, theanti-fuse structure 100 includes a lightly-doped drain (LDD) 132. In the preferred embodiment, theanti-fuse structure 100 is assumed to be a structure of n-type conductivity, therefore thedoped region 130 and theLDD 132 include n-type dopants. However, those skilled in the art would easily realize that theanti-fuse structure 100 can be formed as a structure of p-type conductivity in accordance with different requirement, and thus thedoped region 130 and theLDD 132 may include p-type dopant. Theelectrode structure 120, which serves as a word line, is electrically connected to aword line contact 140 and thedoped region 130 is electrically connected to a bit line through abit line contact 142. It is noteworthy that according to the preferred embodiment, theanti-fuse structure 100 always includes only onedoped region 130 plus its LDD 132 for providing electrical connection between the word line and the bit line. - Please still refer to
FIG. 2 . Theelectrode structure 120 includes aconductive layer 122 and aninsulating layer 124 sandwiched between theconductive layer 122 and thesubstrate 102. Theconductive layer 122 includes polysilicon in the preferred embodiment, but not limited to this. Theconductive layer 122 can be formed of other conductive materials such as metal. In other words, metal gate approach can be adopted in the preferred embodiment. Theinsulating layer 124 includes exemplarily a silicon oxide layer in the preferred embodiment, however theinsulating layer 124 can include any suitable dielectric material. As shown inFIG. 2 , theinsulating layer 124 extends into thenotch 112. More important, theinsulating layer 124 includes a non-uniform thickness according to the preferred embodiment. Due to the defect and stress at thenotch 112, theinsulating layer 124 may have less thickness near and at thenotch 112 compared to the thickness far away from thenotch 112. Theconductive layer 122 includes afirst part 122 a covering a portion of thesubstrate 102 and a portion of theSTI 110. More important, theconductive layer 122 includes asecond part 122 b extended from thefirst part 122 a and filling up thenotch 112 as shown inFIG. 2 . In other words, thesecond part 122 b is formed in between theSTI 110 and thesubstrate 102. - Please refer to
FIG. 3 . During programming, a programming voltage is provided and applied to theanti-fuse structure 100, thus achannel region 114 is formed as shownFIG. 3 . It is noteworthy that thesecond part 122 b, that is thenotch 112 filled by theelectrode structure 120, is the most vulnerable part of theelectrode structure 120 because electrical fields concentrate at the sharp profile. Since thesecond part 122 b obtains the highest electrical fields, arupture point 126 of theinsulating layer 124 is formed at thesecond part 122 b, that is formed at thenotch 112, when a programming voltage is applied. Consequently, the anti-fuse 100 is blown and programmed. - According to the
anti-fuse structure 100 and the anti-fuse programming method provided by the first preferred embodiment, thesecond part 122 b of theelectrode structure 120 is formed to fill thenotch 112 and thus the electrical fields concentrate at thesecond part 122 b due the sharp profile of thenotch 112. Accordingly, therupture point 126 of theinsulating layer 124 is easily limited and located at thesecond part 122 b/thenotch 112 during programming. Therefore, theanti-fuse structure 100 provided by the preferred embodiment has an advantage that therupture point 126 of theinsulating layer 124 is always predictably located at thesecond part 122 b/thenotch 112 as expected. Additionally, compared with the conventional insulating layer having constant thickness, theinsulating layer 124 provided by the preferred embodiment can be formed to have a variable thickness and thus the manufacturing process is simplified. - Please refer to
FIGS. 4-6 , whereinFIGS. 4-5 are schematic drawings illustrating an anti-fuse structure provided by a second preferred embodiment of the present invention andFIG. 6 is a schematic drawing illustrating an anti-fuse programming method provided by the second preferred embodiment of the present invention. It should be noted that elements the same in both of the first preferred embodiment and the second preferred embodiment include the same material, and thus those detail are omitted in the interest of brevity. As shown inFIG. 4 , the preferred embodiment first provides asubstrate 202, and thesubstrate 202 includes an insulating structure such as field oxide (FOX)structure 210 thereon. TheFOX structure 210 is formed by performing a thermal oxidation to thesubstrate 202 and therefore at least a bird'sbeak portion 212 is always formed at the edge of theFOX structure 210 as shown inFIG. 4 . - Please refer to
FIG. 5 . Theanti-fuse structure 200 provided by the preferred embodiment includes anelectrode structure 220 formed on thesubstrate 202 and a dopedregion 230 formed in thesubstrate 202 on a side of theelectrode structure 220 opposite to theFOX structure 210. Also, theanti-fuse structure 200 includes aLDD 232. Theelectrode structure 220, which serves as a word line, is electrically connected to aword line contact 240 and the dopedregion 230 is electrically connected to a bit line through abit line contact 242. It is noteworthy that according to the preferred embodiment, theanti-fuse structure 200 always includes only one dopedregion 230 plus itsLDD 232 for providing electrical connection between the word line and the bit line. - Please still refer to
FIG. 5 . Theelectrode structure 220 includes aconductive layer 222 and an insulatinglayer 224 sandwiched between theconductive layer 222 and thesubstrate 202. As shown inFIG. 5 , theelectrode structure 220 covers a portion of thesubstrate 202 and a portion of theFOX structure 210. It is noteworthy that, since a top surface of theFOX structure 210 is higher than a surface of thesubstrate 202, theelectrode structure 220 includes alower part 222 a located on thesubstrate 202 and ahigher part 222 b located on and raised by theFOX structure 210. - Please refer to
FIG. 6 . During programming, a programming voltage is provided and applied to theanti-fuse structure 200, thus achannel region 214 is formed as shownFIG. 6 . However, it is noteworthy that an adjoining boundary between thelower part 222 a and thehigher part 222 b is the most vulnerable part of theelectrode structure 220 because electrical fields concentrate at this twisting configuration. Since the adjoining boundary obtains the highest electrical fields, arupture point 226 of the insulatinglayer 224 is formed at the adjoining boundary between thelower part 222 a and thehigher part 222 b, when a programming voltage is applied. Consequently, the anti-fuse 200 is blown and programmed. It should be noted that the adjoining boundary is formed corresponding to the bird'sbeak 212 of theFOX structure 210, therefore it is also taken that therupture point 226 of the insulatinglayer 224 is formed at the bird'sbeak 212. - According to the
anti-fuse structure 200 and the anti-fuse programming method provided by the second preferred embodiment, the electrical fields concentrate at the bird'sbeak 212/the adjoining boundary of thelower part 222 a and thehigher part 222 b due to this twisting configuration. Accordingly, therupture point 226 of the insulatinglayer 224 is easily limited and located at this adjoining boundary/the bird'sbeak 212 during programming. Therefore, theanti-fuse structure 200 provided by the preferred embodiment has an advantage that therupture point 226 of the insulatinglayer 224 is always predictably located at the bird'sbeak 212/the adjoining boundary of thelower part 222 a and thehigher part 222 b. Additionally, compared with the conventional insulating layer having constant thickness, the insulatinglayer 224 provided by the preferred embodiment can be formed to have a variable thickness and thus the manufacturing process is simplified. - According to the anti-fuse structure and anti-fuse programming method, the rupture point of the insulating layer is located at the notch or at the bird's beak as expected. In other words, the rupture point of the anti-fuse structure is predictably limited. Furthermore, since the rupture point of the insulating layer is located at the notch or at the adjoining boundary where the highest electrical fields are found, the insulating layer provided by the preferred embodiment can be formed to have a variable thickness and thus the manufacturing process is simplified.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (18)
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CN109346435A (en) * | 2016-12-02 | 2019-02-15 | 乐清市风杰电子科技有限公司 | The manufacturing method of programmable polysilicon fuse structure |
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US10580780B2 (en) | 2018-06-11 | 2020-03-03 | United Microelectronics Corp. | Semiconductor structure and method of forming the same |
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