TWI529936B - Semiconductor structure and fabrication method thereof - Google Patents

Description

Semiconductor structure and its manufacturing method

The present invention relates to a semiconductor structure and a method of making same. In particular, the present invention relates to a semiconductor structure having a fully shallow doped drain region sandwiched between a cap layer and a doped epitaxial material, with improved component reliability.

In order to increase the carrier mobility of the semiconductor structure, it is an advanced practice to apply stress to the gate channel. For example, compressive stress or tensile stress can be applied to the gate channel as needed. If a compressive stress is required for the gate channel, the current method is to use a germanium epitaxial material. By virtue of the principle that the germanium atoms in the epitaxial material are larger than the germanium atoms, an appropriate compressive stress can be generated for the gate channel.

It is currently known that the closer the applied stress source is to the gate channel, the more effective the semiconductor structure is to apply stress in the gate channel to more effectively adjust the carrier mobility. The current widely used practice is in the gate. A recess is etched near the pole structure, preferably the recess has a tip that penetrates into the gate passage to effectively communicate stress into the gate passage. However, such current solutions affect the reliability of components.

Therefore, there is still a need for a novel semiconductor structure with better component reliability.

In view of this, the present invention thus proposes a novel semiconductor structure and fabrication method that has better component reliability. For example, the novel semiconductor structure of the present invention can have a semiconductor structure sandwiched between a cap layer and a doped epitaxial material, a fully shallow doped drain region, with improved component reliability. Alternatively, the novel semiconductor structure of the present invention may also have a cap layer for isolating the shallow doped drain region from the metal germanide such that the shallow doped drain region does not contact the metal germanide to become a complete shallow doped drain Area.

The invention first proposes a semiconductor structure. The semiconductor structure of the present invention comprises at least a substrate, a gate structure, at least one recess, a doped epitaxial material, a shallow doped drain region, a cap layer and a metal halide. The gate structure is on the substrate. At least one of the pockets is located in the substrate adjacent to the gate structure. The doped epitaxial material fills at least one of the pockets. The shallow doped drain region is located on top of the doped epitaxial material. The cap layer comprises an undoped epitaxial material on the doped epitaxial material and overlying the doped epitaxial material.

In an embodiment of the invention, the semiconductor structure of the present invention further comprises an interlayer dielectric layer and a contact plug. The interlayer dielectric layer covers the gate structure and the cap layer. The contact plug is located in the interlayer dielectric layer and electrically connects the cap layer.

In another embodiment of the invention, the semiconductor structure of the present invention further comprises a metal halide that at least partially covers the cap layer and is completely covered by the contact plug. The cap layer isolates the shallow doped drain region from the metal telluride such that the shallow doped drain region does not contact the metal telluride.

In another embodiment of the invention, the semiconductor structure of the present invention further comprises a metal halide on the cap layer that completely covers the cap layer.

In another embodiment of the invention, the gate structure includes a spacer that simultaneously contacts the cap layer and the shallow doped drain region.

In another embodiment of the invention, the gate structure further includes an outer spacer. The outer spacer is located outside the spacer and covers the cap layer together with the metal halide.

In another embodiment of the invention, at least one of the pockets in turn includes a tip that extends to below one of the gate structures.

In another embodiment of the invention, the shallowly doped drain region also overlaps the tip of at least one of the pockets.

In another embodiment of the invention, the shallowly doped drain region completely overlaps the top of the doped epitaxial material and extends below the gate structure.

In another embodiment of the invention, the gate structure may be a P-type MOS gate or an N-type MOS gate.

In another embodiment of the invention, the doped epitaxial material may comprise two different tetravalent elements, such as lanthanum and cerium, or lanthanum and carbon.

In another embodiment of the invention, the shallowly doped drain region completely overlaps the top of the doped epitaxial material and extends below the gate structure.

The present invention further provides a method of forming a semiconductor structure. First, a substrate is provided. The substrate has a gate structure on the substrate and at least one recess in the substrate adjacent to the gate structure. Next, a layer of doped epitaxial material filled with at least one recess is formed. Then, a doping step is performed to form a complete shallow doped drain region on top of the doped epitaxial material layer. Next, a cap layer comprising an undoped epitaxial material is formed over the shallow doped drain region and overlying the doped epitaxial material.

In an embodiment of the invention, the method of forming a semiconductor structure further includes forming an outer spacer that surrounds the gate structure and partially covers the cap layer.

In another embodiment of the present invention, after forming the outer gap wall, the following steps are further included. A heavily doping step is first performed to form a source/drain region in the cap layer and the doped epitaxial material layer. An interlevel dielectric layer is formed to cover the gate structure and the cap layer.

In another embodiment of the invention, the method of forming a semiconductor structure further comprises the following steps. A metal halide that completely covers the cap layer is formed prior to forming the interlayer dielectric layer. The contact plug is further formed such that the contact plug passes through the interlayer dielectric layer, partially covers the metal telluride on the cap layer, and electrically connects the cap layer.

In another embodiment of the present invention, after the formation of the interlayer dielectric layer, the following steps are further included. The metal halide is first formed to form a contact plug such that the contact plug passes through the interlayer dielectric layer, completely covers the metal halide on the cap layer and electrically connects the cap layer.

In another embodiment of the invention, the doping step is an oblique implantation step such that the shallow doped drain region and the top of one of the doped epitaxial materials are completely overlapped and extend below the gate structure.

In another embodiment of the invention, the shallowly doped drain region overlaps the tip of at least one of the recesses and the tip extends below the gate structure.

In another embodiment of the invention, the gate structure is a P-type MOS gate or an N-type MOS gate.

In another embodiment of the invention, the doped epitaxial material may comprise two different tetravalent elements, such as lanthanum and cerium, or lanthanum and carbon.

SUMMARY OF THE INVENTION The present invention provides a novel semiconductor structure having a semiconductor structure sandwiched between a cap layer and a doped epitaxial material, a fully shallow doped drain region, with improved component reliability. Alternatively, the novel semiconductor structure of the present invention may also have a cap layer for isolating the shallow doped drain region from the metal telluride such that the shallow doped drain region does not contact the metal germanide and becomes a complete shallow doped germanium. Polar zone. The complete shallow doped drain region helps to increase the saturation current value (I _sat ) of the semiconductor component.

The present invention first provides a method of forming a semiconductor structure that provides an unreduced, intact shallow doped drain region. Referring to Figures 1 through 9, a possible method of forming a semiconductor structure of the present invention is illustrated. First, referring to Fig. 1, a substrate 101 is provided. Substrate 101 can be a doped semiconductor substrate, such as a doped germanium. Further, among the base material 101, a plurality of shallow trench isolations 102 and doping wells (not shown) for electrical isolation are formed in advance.

For the step of forming the shallow trench isolation 102, reference may be made to the following method. First, a plurality of trenches (not shown) for forming shallow trench isolation are etched into the substrate 101 using a hard mask (not shown). The semiconductor device region 103 of the substrate 101 can be used as a PMOS or as an NMOS, and can be fabricated in a subsequent process by, for example, embedding germanium (SiGe) to prepare a PMOS, or in combination with germanium carbon (SiC). The NMOS is prepared to improve the MOS current drive to improve the performance of the MOS. Subsequently, an insulating material (not shown) is filled into the previously formed trench (not shown), and the hard mask is removed after planarization removes excess insulating material (not shown) (not shown) ), and a shallow trench isolation 102 is obtained.

Next, a gate structure 110 is formed over the semiconductor device region 103 of the substrate 101. The gate structure 110 may be a P-type MOS gate or an N-type MOS gate. The gate structure 110 includes an inner spacer 111, a gate dielectric layer 112, a high dielectric constant layer (not shown) as needed, a barrier layer (not shown) as needed, and a gate material layer 113. A cap layer (not shown), as needed. The gate dielectric layer 112 is in direct contact with the substrate 101 and is electrically insulated from the substrate 101 as the gate structure 110. Depending on the situation, it is usually also possible to perform an implantation step of a shallow doped drain (LDD) (not shown) on the NMOS.

If the gate structure 110 is a germanium gate, the gate dielectric layer 112 may comprise a germanium compound such as hafnium oxide, hafnium oxynitride, tantalum nitride or a combination thereof. If the gate structure 110 is a metal gate, the gate dielectric layer 112 may comprise an oxide such as hafnium oxide. The high dielectric constant layer as required may comprise a material having a high dielectric constant, for example, may be selected from hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), niobium niobate Oxygen compound (hafnium silicon oxynitride, HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (yttrium) Oxide, Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium Oxide, HfZrO ₄ ), strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium titanate A group consisting of barium strontium titanate, Ba _x Sr _1-x TiO ₃ , BST. The barrier layer serves as an isolation gate material layer 113 and a bottom layer, which may comprise a metal compound such as titanium nitride or tantalum nitride.

Subsequently, at least one recess is formed in the substrate 101 adjacent to the gate structure 110, and the method of forming the same can be referred to the following steps. First, referring to FIG. 2, a material layer 119 is uniformly covered with the substrate 101, the shallow trench isolation 102, and the gate structure 110. The material layer 119 may comprise a bismuth compound such as cerium oxide, cerium oxynitride, cerium nitride or a combination of the above. Next, referring to FIG. 3, the material layer 119 is patterned by a suitable yellow light and etching step to form a protective layer covering other regions, and at the same time, the material layer 119 in the semiconductor device region 103 is converted. The spacer 114 surrounding the spacer 111 in the gate structure 110 becomes a part of the gate structure 110. Preferably, this etching step can also be used to further remove a portion of the substrate 101 to obtain at least one recess 120. Alternatively, at least one recess 120 may be obtained by successively performing a separate etching step to remove a portion of the substrate 101.

The etching method may be dry etching in combination with wet etching, and the recess 120 may have a special three-dimensional shape depending on etching conditions. For example, a dry etch is performed first, followed by a wet etch step, and the recess 120 extends laterally to partially occupy the gate via 104 under the gate structure 110. At the same time, the portion of the recess 120 below the gate structure 110 may also be wedge shaped such that the recess 120 includes a tip 121 below the gate structure 110.

Next, please refer to FIG. 4, after the cleaning process is completed, the doped epitaxial material 122 can be filled into the cavity 120 by epitaxy. Optionally, the doped epitaxial material 122 may be subjected to a hydrogen prebaking step prior to growth, or the hydrogen prebaking step and the in-situ step of the doping epitaxial material 122 growth step. . The doped epitaxial material 122 will typically comprise at least two different tetravalent elements with suitable dopants. A tetravalent element such as lanthanum and cerium, or carbon and lanthanum. The dopants are, for example, boron or phosphorous. Additionally, the doped epitaxial material 122 may contain several different portions. For example, a buffer layer (not shown) located at the bottom of the cavity 120 may contain a low concentration of germanium, no boron or a small amount of boron to reduce the difference between the different crystal lattices of the substrate 101; the main layer (not shown), A high concentration of germanium and a large amount of boron may be included, primarily as a source of stress in the gate channel 104.

Then, referring to FIG. 5, a shallow doped drain (LDD) implantation step can be performed on the semiconductor device region 103 including the recess 120, for example, a PMOS region. For example, a yellow light step is first used to define a PMOS region that requires a shallow doped drain (LDD) implant step. The implantation step of the shallow doped drain may be a right angle or tilt implant step to form a shallow doped drain region 123 in the doped epitaxial material 122 on both sides of the gate structure 110. . The shallowly doped drain region 123 is typically located on top of the doped epitaxial material 122, and preferably overlaps the top of the doped epitaxial material 122 and extends to the spacer 114 or even to the substrate below the inner spacer 111. 101.

In an embodiment of the invention, the implant angle of the shallow doped drain can be adjusted such that the shallow doped drain region 123 overlaps the tip 121. Preferably, the shallowly doped drain region 123 can also extend into the substrate 101 below the spacers 114. Pocket implant or halo doping can also be performed as needed.

Continuing, please refer to FIG. 6, and a cap layer is formed on the doped epitaxial material 122 and along the spacer 114 to completely cover the doped epitaxial material 122 and the shallow doped drain region 123. The shallow doped drain region 123 is located below the cap layer 124, and the spacer 114 is simultaneously in contact with the cap layer 124 and the shallow doped drain region 123, and the shallow doped drain region 123 is in the doped epitaxial material. Above one of the bottoms 130 of the 122, that is, the shallowly doped drain region 123 is sandwiched between the bottom 130 of the doped epitaxial material 122 and the cap layer 124. The cap layer 124 can comprise an undoped epitaxial material, such as germanium with a low concentration of germanium, or no germanium. However, the cap layer 124 is substantially free of dopants.

Referring again to FIG. 7, an outer spacer 115 surrounding the gate structure 110 may be further formed outside the spacer 114 of the gate structure 110 such that the outer spacer 115 may straddle the cap layer 124. The outer spacer 115 of the gate structure 110 partially covers the cap layer 124. The step of forming the outer spacers 115 can be as follows. First, a layer of material (not shown) is uniformly covered over the shallow trench isolation 102, the gate structure 110, and the cap layer 124. The material layer may comprise a compound of cerium, such as cerium oxide, cerium oxynitride, cerium nitride or a combination of the above. Then, through a suitable etching step, the material layer (not shown) It is converted into a spacer 115 surrounding the spacer 114 of the gate structure 110 to become a part of the gate structure 110.

Then, referring to FIG. 8, a doping step is performed on the cap layer 124 to form a source doping region 125 and a drain doping region 126. Preferably, the source/drain doping steps pass through the cap layer 124 and the shallow doped drain region 123 to be deeply doped into the epitaxial material 122. In addition, due to the shielding of the outer spacers 115, the source doping region 125 and the drain doping region 126 do not completely overlap the capping layer 124 and the shallow doped drain region 123, while the source doping regions 125 and 汲The highly doped region 126 may also not contact the spacers 114. An annealing step may be continued after the heavy doping step, as the case requires. The annealing step may be a conventional source/drain annealing step, such as a rapid annealing step (RTA) or laser annealing, etc., to activate the previously implanted dopant and form the source 125 in the substrate 101. Bungee 126.

Next, referring to FIG. 9, a metal halide layer 127 covering the doped epitaxial material 122 may be formed as needed to reduce the sheet resistance of the semiconductor device contact plug (not shown). In general, the metal telluride layer 127 will be on the surface of the exposed cap layer 124 and will cover the cap layer 124 with the outer spacers 115. The manner in which the metal telluride layer 127 is formed can be referred to the steps shown below. First, a suitable metal (not shown), such as titanium, nickel or cobalt, is used to completely cover the shallow trench isolation 102, the gate structure 110 and the surface of the cap layer 124. Subsequently, a heating step is performed to react the metal with ruthenium into a metal ruthenide layer 127. Finally, the unreacted metal is removed and a further heating step can be carried out.

Since only the cap layer 124 contains germanium, and the shallow trench isolation 102 and the surface of the gate structure 110 do not contain germanium, the metal will only directly react with the cap layer, and the metal germanide layer 127 will only be formed to be exposed. The surface of the cap layer 124. If the height of the cap layer 124 is higher than the shallow trench isolation 102, a metal telluride layer 127 is also formed over the shallow trench isolation 102, ie, the side of the cap layer 124. In addition, since the cap layer 124 isolates the shallow doped drain region 123 from the metal germanide 127, the shallow doped drain region 123 does not contact the metal germanide 127.

Alternatively, please refer to FIG. 10, and the metal germanide layer 127 may be formed after the interlayer dielectric layer 129 is formed, as needed, so that the contact plugs 128 in the interlayer dielectric layer 129 can completely cover the metal telluride. Layer 127 is electrically coupled to cap layer 124 to reduce the sheet resistance of semiconductor component contact plug 128. For example, the interlayer dielectric layer 129 is first formed to completely cover the cap layer 124 and the gate structure 110. Then, the interlayer dielectric layer 129 is etched to form a contact hole (not shown) of the exposed cap layer 124. The contact hole (not shown) may be filled with a suitable metal (not shown), such as titanium, nickel or cobalt, and subjected to a heating step to form a metal telluride layer 127, and the unreacted metal is removed and replaced. The plug metal is suitably contacted to form a contact plug 128 that passes through the interlayer dielectric layer 129. Alternatively, the metal forming the metal telluride layer 127 remains in the contact hole (not shown) for use as the contact plug 128.

Subsequently, other subsequent necessary semiconductor steps can be performed, such as replacing the gate material layer 113 with a suitable metal material to form a metal gate, a contact hole forming step, or a contact plug forming step, etc. . Use The contact plugs (not shown) of the source 125 and the drain 126 may be asymmetrical in shape. For example, one of them may be square and the other may be a continuously extending strip. These follow-up necessary processes are known to those skilled in the art and are therefore not described in any way.

Incidentally, one of the features of the present invention is that the shallow doped drain (LDD) implantation step of the semiconductor device region 103 must be performed after the etching step of the recess 120, so that the etching step of the recess 120 does not affect the shallowness at all. The implantation step of the doped drain (LDD), in addition, since the cap layer 124 isolates the shallow doped drain region 123 from the metal germanide 127, the subsequently formed metal germanide 127 is not consumed or contacted shallow. The drain region 123 is doped so that a semiconductor structure 100 having a completely shallow doped drain region can be obtained. If the etching step of the recess 120 is performed after the implantation step of the shallow doped drain (LDD), no matter how well the distribution of the shallow doped drain (LDD) is before, the etching step through the recess 120 After that, it will definitely damage the distribution profile of the shallow doped drain (LDD), and even severely remove the shallow doped drain (LDD) region, resulting in a significant deficiency of the shallow doped drain (LDD) region, which will lead to semiconductors. The saturation current value (I _sat ) of the component is too small, which seriously affects the reliability of the semiconductor component. Another feature of the present invention is that the complete shallow doped drain region extends into the substrate below the spacer to contact the gate channel without having to reduce any spacers in the gate structure.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Semiconductor structure

101‧‧‧Substrate

102‧‧‧Shallow trench isolation

103‧‧‧Component area

104‧‧‧ gate channel

110‧‧‧ gate structure

111‧‧‧Intervaling wall

112‧‧‧ gate dielectric layer

113‧‧‧ gate material layer

114‧‧‧ clearance

115‧‧‧ outer spacer

119‧‧‧Material layer

120‧‧‧ recess

121‧‧‧ tip

122‧‧‧Doped epitaxial material

123‧‧‧Shallowly doped bungee zone

124‧‧‧cap layer

125‧‧‧ source doped area

126‧‧‧汲polar doped area

127‧‧‧metal telluride layer

128‧‧‧Contact plug

129‧‧‧Interlayer dielectric layer

130‧‧‧ bottom

Figures 1 through 10 illustrate a possible method of forming the semiconductor structure of the present invention.

101. . . Substrate

102. . . Shallow trench isolation

103. . . Component area

104. . . Gate channel

110. . . Gate structure

111. . . Inner spacer

112. . . Gate dielectric layer

113. . . Gate material layer

114. . . Clearance wall

115. . . Outer spacer

120. . . Pocket

121. . . Cutting edge

122. . . Doped epitaxial material

123. . . Shallow doped bungee zone

124. . . Cap layer

125. . . Source doping region

126. . . Bipolar doping zone

Claims (20)

A semiconductor structure comprising: a substrate; a gate structure on the substrate; at least one recess located in the substrate adjacent to the gate structure; a doped epitaxial material filling the at least one a shallow doped drain region located in the doped epitaxial material and on top of one of the doped epitaxial materials; and a cap layer comprising an undoped epitaxial material and located in the doped The doped epitaxial material is overlaid on the impurity epitaxial material, wherein the shallow doped drain region is sandwiched between one of the bottoms of the doped epitaxial material and the cap layer. The semiconductor structure of claim 1, further comprising: at least partially covering a metal halide of the cap layer, wherein the cap layer isolates the shallow doped drain region from the metal germanide such that the shallow doped germanium The polar region does not contact the metal halide. The semiconductor structure of claim 2, further comprising: an interlayer dielectric layer covering the gate structure and the cap layer; and a contact plug located in the interlayer dielectric layer and electrically connecting the cap layer, wherein The metal halide is located on the cap layer and completely covers the cap layer. The semiconductor structure of claim 2 further includes: An interlayer dielectric layer covering the gate structure and the cap layer; a contact plug located in the interlayer dielectric layer and electrically connecting the cap layer; and an outer spacer surrounding the gate structure, wherein The metal halide is disposed on the cap layer such that the contact plug completely covers the metal halide, and the outer spacer layer, the interlayer dielectric layer and the metal halide cover the cap layer. The semiconductor structure of claim 1, further comprising a spacer between the gate structure and the outer spacer, and the cap layer covers the shallow doped drain region together with the spacer. The semiconductor structure of claim 1, wherein the gate structure further comprises a spacer that simultaneously contacts the cap layer and the shallow doped drain region. The semiconductor structure of claim 1, wherein the at least one recess further comprises a tip located below the gate structure and the shallow doped drain region overlaps the tip. The semiconductor structure of claim 1 wherein the shallowly doped drain region extends below the gate structure. The semiconductor structure of claim 1, wherein the gate structure is one of a P-type MOS gate and an N-type MOS gate. The semiconductor structure of claim 1 wherein the doped epitaxial material comprises two different tetravalent elements. The semiconductor structure of claim 1 wherein the shallowly doped drain region completely overlaps the top of the doped epitaxial material and extends below the gate structure. A method of forming a semiconductor structure, comprising: providing a substrate having a gate structure on the substrate, and at least one recess in the substrate adjacent to the gate structure; forming a doping a layer of epitaxial material filling the at least one recess; performing a doping step to form a shallow doped drain region on top of one of the doped epitaxial material layers; and forming a cap layer comprising An undoped epitaxial material is disposed over the shallow doped drain region and covering the doped epitaxial material, wherein the shallow doped drain region is located in the doped epitaxial material and is sandwiched between the doped epitaxy Between one of the bottoms of the crystalline material and the cap layer. The method of claim 12, wherein the method of forming a semiconductor structure further comprises: forming an outer spacer surrounding the gate structure and partially covering the cap layer. The method of claim 13, wherein after forming the outer spacer, further comprising: performing a heavily doping step, and forming a source/drain in the cap layer and the doped epitaxial material layer And forming an interlayer dielectric layer to cover the gate structure and the cap layer. The method of claim 14, wherein the method further comprises: forming a metal germanide prior to forming the interlayer dielectric layer to completely cover the cap layer; and forming a contact plug such that the contact plug passes through the contact plug An interlayer dielectric layer covering the metal halide on the cap layer and electrically connecting the cap layer. The method of claim 14, wherein after forming the interlayer dielectric layer, further comprising: forming a metal germanide and a contact plug, such that the contact plug passes through the interlayer dielectric layer and is completely covered. The metal halide on the cap layer and electrically connects the cap layer. The method of claim 12, wherein the doping step is an oblique implantation step such that the shallow doped drain region completely overlaps the top of the doped epitaxial material and extends to the gate structure Below. The method of claim 12, wherein the shallow doped drain region overlaps a tip end of the at least one recess and the tip extends below the gate structure. A method of forming a semiconductor structure as claimed in claim 12, wherein the gate structure is one of a P-type MOS gate and an N-type MOS gate. A method of forming a semiconductor structure as claimed in claim 12, wherein the gate structure comprises an inner a spacer, and the shallow doped drain region extends below the inner spacer.