JP2001308283A - Semiconductor device and method of manufacturing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a gate insulating film having a desired breakdown voltage without increasing manufacturing processes by applying a step-off process for an alignment mark to the formation of an anti fuse. SOLUTION: In a silicon substrate 11, a first recess 16 for element isolation, a second recess 13 for an alignment mark part, and a third recess 14 for an anti fuse part are formed simultaneously. After the silicon oxide film is formed on the entire surface, the silicon oxide film in the second, and the third recesses 13, 14 is removed. The gate insulating film 18 is then formed on the entire surface and a polysilicon film 19 is formed on this gate insulating film 18. By selectively removing this polysilicon film 19 and the gate insulating film 18, a gate electrode 22, the alignment mark part 23, and the gate electrode 24 for the anti fuse part are formed on the element region, in the second recess 13, and in the bottom surface of the third recess 14 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device relating to a fuse / antifuse and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been highly miniaturized. According to this, a method of forming an element isolation region for isolating an element is based on a conventional LOCOS (Local Oxidation Of).
STI (Shallow Trench Isolati) instead of Silicon
on) law has become mainstream. However, the flatness of the film surface is extremely high in the STI method. For this reason, in the subsequent formation of the gate electrode, a step for forming a step for the alignment mark portion is required.

FIGS. 28 to 33 are sectional views showing the steps of manufacturing a semiconductor device according to the prior art. Hereinafter, a method of manufacturing a semiconductor device according to the related art will be described.

First, as shown in FIG. 28, a lithography technique and an RIE (Reactive Ion Etching) method are used.
In the silicon substrate 41, a first concave portion 42 serving as an element isolation region is formed, and a second concave portion 43 for an alignment mark used in a later lithography step is formed.

Next, as shown in FIG. 29, for example, a silicon oxide film 45 is formed on the entire surface.
At 5, the first and second concave portions 42 and 43 are buried. Thereafter, the silicon oxide film 45 is removed using a CMP (Chemical Mechanical Polish) method until the surface of the silicon substrate 41 is exposed. As a result, S
An element isolation region 46 having a TI structure is formed.

Next, as shown in FIG. 30, after a resist film 47 is formed on the entire surface, the resist film 47 is patterned using a lithography technique and an RIE method.
Using this patterned resist film 47 as a mask, the silicon oxide film 45 in the second concave portion 43 is removed by wet etching. Thereby, the alignment mark portion 53 is formed in the second concave portion 43. After that, the resist film 47 is removed. In the following description, the silicon oxide film 4 embedded in the second concave portion 43 will be described.
The step of removing 5 is referred to as a step forming step.

Next, as shown in FIG. 31, a gate insulating film 48 is formed on the entire surface, and a polysilicon film 49 is formed on the gate insulating film 48. This polysilicon film 49
A tungsten film 50 is formed thereon, and a silicon nitride film 51 is formed on the tungsten film 50.

Next, as shown in FIG. 32, the silicon nitride film 51, the tungsten film 50, the polysilicon film 49, and the gate insulating film 48 are selectively removed by using the lithography technique and the RIE method. As a result, the gate electrode 52 is formed on the predetermined element region 46a. Here, the gate insulating film of the gate electrode 52 is indicated by reference numeral 48a.

Next, as shown in FIG. 33, a gate side wall 55 is formed on the side surface of the gate electrode 52 using a known technique, and the silicon substrate 41 at both lower ends of the gate electrode 52 is formed.
A source / drain region 56 is formed on the surface of the substrate. Next, an interlayer insulating film 57 is formed on the entire surface, and a contact plug 58 and an upper wiring layer 59 are formed. Thereafter, an interlayer insulating film 60 is further formed on the entire surface.

As described above, when the tungsten film 50 or the like is used as a part of the gate electrode 52, the reflectivity of the film is high, so that it is difficult to read the difference in film quality of the lower layer by an optical method. For this reason, if the step of forming the alignment mark portion 53 shown in FIG. 30 is omitted, if a method having a high degree of flatness of the film surface such as the STI method is used, the alignment mark portion 53 has no step. Since it is not formed, the alignment mark portion 53 cannot be read by an optical method. Therefore, the problem of misalignment between the element isolation region 46 (or the element region 46a) and the gate electrode 52 becomes serious.

As described above, in order to avoid the problem of misalignment, the lithography step and the etching step included in the step forming step are indispensable. However,
Since these steps are used only for stepping the alignment mark portion 53, it has been desired that these steps be omitted or effectively utilized.

[0012]

On the other hand, for example, a DRAM
(Dynamic Random Access Memory) and the like often include a relief circuit for replacing defective cells with spare cells in order to improve product yield. Therefore, conventionally, a fuse of a type in which a wiring made of aluminum or the like is burned off by a laser has been used for determining a replacement cell. On the other hand, an antifuse that makes a determination by destroying a gate insulating film at a specific location has been proposed.

The antifuse is expected to have many advantages, such as a reduction in the area occupied in the chip and the replacement of the last defective cell after encapsulation of the package. The antifuse breaks a desired gate insulating film by applying a voltage higher than a breakdown withstand voltage to make it conductive. For this reason, antifuse is usually
The circuit is connected to a high voltage generating circuit for destruction and a determination circuit for detecting a destructed or non-destructed state of a specific antifuse portion. Therefore, when the antifuse portion is destroyed, the gate insulating film of the determination circuit portion is also damaged to some extent. Therefore, it has been desired that the antifuse portion can be broken at a somewhat low voltage, and damage to the determination circuit portion and others is reduced as much as possible.

In order to suppress an increase in the number of manufacturing steps, it is desirable that the gate insulating film in the antifuse portion is formed simultaneously with the gate insulating film of the MOS transistor. However, it has been difficult to form a low-breakdown-voltage gate insulating film in the antifuse portion simultaneously with a highly reliable gate insulating film used for a normal transistor or the like. Therefore, it has been difficult to commercialize an antifuse using a gate insulating film formed for a transistor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to apply a step for aligning marks to the formation of an antifuse without increasing the number of manufacturing steps. Another object of the present invention is to provide a semiconductor device capable of forming a gate insulating film having a desired breakdown voltage and a method of manufacturing the same.

[0016]

The present invention uses the following means to achieve the above object.

A semiconductor device according to the present invention comprises a concave portion formed in a semiconductor substrate, a first gate insulating film selectively formed on the semiconductor substrate, and a second gate insulating film formed on at least a bottom surface of the concave portion. , A first conductive film formed on the first gate insulating film, and a second conductive film formed on the second gate insulating film.

The second gate insulating film and the second conductive film are formed on the bottom surface of the concave portion, both side surfaces or one side surface of the concave portion, and the semiconductor substrate, and are formed on the semiconductor substrate. The surface and the film surface of the second conductive film on the semiconductor substrate may be at the same height.

The second gate insulating film may be formed at a corner of the recess.

[0020] An insulating film may be formed on the second conductive film, and the concave portion may be filled with the insulating film, the second gate insulating film and the second conductive film. further,
The concave portion may be filled with the second gate insulating film and the second conductive film, and a film surface of the second conductive film may be substantially flat.

[0021] The semiconductor substrate may be an SOI substrate.

An element isolation region formed in the semiconductor substrate and the second gate insulating film and the second conductive film are drawn out to above the element isolation region. A contact electrically connected to the film;
The semiconductor device may further include a wiring electrically connected to the contact.

A plurality of recesses are formed, the plurality of recesses are filled with the second gate insulating film and the second conductive film, and the surface of the second conductive film is substantially flat. Is also good.

A plurality of gate electrodes made of the second conductive film may be formed in the recess.

[0025] The impurity concentration of the second conductive film may be higher than the impurity concentration of the semiconductor substrate.

The second insulating film functions as an insulating film for an antifuse portion or a capacitor element.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming first, second, and third concave portions in a semiconductor substrate;
The first, second, and third recesses are filled with an insulating film, and the surface of the insulating film is planarized until the surface of the semiconductor substrate is exposed, so that an element isolation region is formed in the first recess. A forming step, a step of forming an alignment mark portion in the second recess by removing the insulating film in the second and third recesses, and a step of forming a gate insulating film on the entire surface. Forming a conductive film on the gate insulating film; selectively removing the conductive film to form a first gate electrode on the semiconductor substrate; Forming a second gate electrode.

[0028] A gate insulating film may be formed on the entire surface while a part of the insulating film formed in the third recess remains.

[0029] The second gate electrode may be formed on a bottom surface of the third concave portion, both side surfaces or one side surface of the third concave portion, and on the semiconductor substrate.

[0030] The second gate electrode may be formed so as to fill the third recess.

[0031] The second gate electrode may be formed so as to extend from the inside of the third recess to above the element isolation region, and a contact may be formed on the second gate electrode on the element isolation region.

[0032] A plurality of the third concave portions may be formed. Further, a plurality of the second gate electrodes may be formed in the third recess.

[0033] The impurity concentration of the conductive film may be higher than the impurity concentration of the semiconductor substrate.

The second gate electrode functions as a gate electrode for an antifuse section or a capacitor element.

[0035]

Embodiments of the present invention will be described below with reference to the drawings. For this explanation,
Common parts are denoted by common reference symbols.

[First Embodiment] The method of manufacturing a semiconductor device according to the first embodiment is characterized in that a concave portion (step) of an alignment mark portion is formed and a concave portion of an antifuse portion is formed at the same time. Thereby, the lithography process and the etching process in forming the concave portion of the alignment mark portion are effectively used.

FIGS. 1 to 6 are sectional views showing the steps of manufacturing a semiconductor device according to the first embodiment of the present invention. Hereinafter, a method for manufacturing the semiconductor device according to the first embodiment will be described.

First, as shown in FIG. 1, a first recess 1 serving as an element isolation region is formed in a silicon substrate 11 by using a lithography technique and an RIE (Reactive Ion Etching) method.
2 are formed, and the second concave portion 13 of the alignment mark portion and the third concave portion 14 of the antifuse portion used in the subsequent lithography process are formed at the same time.

Next, as shown in FIG. 2, for example, a silicon oxide film 15 is formed on the entire surface.
Then, the first, second, and third concave portions 12, 13, and 14 are buried. Then, CMP (Chemical Mechanical Polish)
Using the method, silicon oxide film 15 is removed until the surface of silicon substrate 11 is exposed. As a result, the STI structure element isolation region 16 is formed in the first recess 12.

Next, as shown in FIG. 3, a resist film 17 is formed on the entire surface and patterned. Using this patterned resist film 17 as a mask, the silicon oxide film 15 in the second concave portion 13 and the third concave portion 14 is removed by wet etching. Thereby, the second
An alignment mark portion 23 is formed in the concave portion 13. After that, the resist film 17 is removed.

Next, as shown in FIG. 4, a gate insulating film 18 is formed on the entire surface, and a polysilicon film 19 is formed on the gate insulating film 18. Here, the gate insulating film 18
Is formed of, for example, one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Thereafter, a tungsten film 20 is formed on the polysilicon film 19, and a silicon nitride film 21 is formed on the tungsten film 20.

Next, as shown in FIG. 5, the silicon nitride film 21, the tungsten film 20, the polysilicon film 19, and the gate insulating film 18 are formed by using the lithography technique and the RIE method.
Is selectively removed. Thereby, the predetermined element region 1
6a, a first gate electrode 22 is formed,
The second gate electrode 24 for the antifuse portion is formed simultaneously on the bottom surface of the third recess 14. Here, the gate insulating film of the first gate electrode 22 is denoted by reference numeral 18a, and the gate insulating film of the second gate electrode 24 is denoted by reference numeral 18b.
Note that the gate insulating film 18 may be left on the entire surface of the substrate without being removed.

Next, as shown in FIG. 6, gate sidewalls 25 are formed on the side surfaces of the first and second gate electrodes 22 and 24 using a known technique. Source / drain regions 26 are formed on the surface of silicon substrate 11 at the lower end. Next, an interlayer insulating film 27 is formed on the entire surface, and a contact plug 28 and an upper wiring layer 29 for connecting the second gate electrode 24 to another element are formed. After that, an interlayer insulating film 30 is formed on the entire surface.

According to the first embodiment of the present invention, the gate insulating film 18b for antifuse is formed in the third recess 1
4 is formed on the bottom surface. The bottom surface of the third recess 14 is damaged by RIE when the recesses 12, 13, 14 are formed. Therefore, the breakdown voltage of the gate insulating film 18b formed in the recess 14 can be reduced as compared with the gate insulating film 18a of the transistor formed on the surface of the substrate 11. Therefore, without applying an extremely high voltage, the gate insulating film 18 for antifuse can be used.
Only b can be destroyed. This makes it possible to reduce damage to the gate insulating film 18a of a transistor such as a determination circuit. Therefore,
High reliability of the transistor can be maintained, which can contribute to an improvement in yield.

The lithography and etching steps in the formation of the concave portion 13 of the alignment mark portion 23 are shared with the formation of the concave portion 14 for the antifuse portion, and the gate insulating film 18b of the antifuse portion is simultaneously formed with the gate insulating film 18a for the transistor. Is formed. Therefore, it is not necessary to newly add a manufacturing process for providing the antifuse portion. Therefore, the cost of the semiconductor device can be reduced.

In the first embodiment, the lower end of the resist film 17 for forming the antifuse third recess 14 shown in FIG. 3 is located outside the upper end of the third recess 14. are doing. For this reason, in the etching process,
The silicon oxide film 15 in the third recess 14 is completely removed. However, the positional relationship between the third recess 14 and the lower end of the resist film 17 is not limited to this.

For example, when the lower end of the resist film 17 is located inside the upper end of the third recess 14, a part of the silicon oxide film 15 remains in the third recess 14 as shown in FIG. be able to. By the way, when forming the gate electrode, the gate insulating film at the end of the gate electrode may be damaged by, for example, a process such as RIE, so that the variation in the breakdown voltage of the gate electrode may not be completely adjusted. However, according to the structure shown in FIG. 7, the remaining silicon oxide film 15 is present at the end of the gate electrode 24. Therefore, the insulating film made of the silicon oxide film 15 can suppress the destruction at the end of the gate electrode 24,
It is possible to adjust the variation in the breakdown voltage of the gate insulating film 18b.

[Second Embodiment] The second embodiment is an example in which the shape of the gate electrode for antifuse is deformed in order to positively use the corners of the concave portion for antifuse. Since the second embodiment is the same as the manufacturing method of the first embodiment, only the structure different from that of the first embodiment will be described.

As shown in FIG. 8, the gate electrode 2 is formed on the bottom and side surfaces of the concave portion 14 and on the semiconductor substrate 11 to cover the corner portions 14a and 14b of the concave portion 14 for antifuse.
4 are formed.

As shown in FIG. 9, when a plurality of recesses 14 are provided, the bottom and side surfaces of the recesses 14 extend over the plurality of recesses 14 to cover the corner portions 14a and 14b of the antifuse recesses 14. Then, a gate electrode 24 is formed on the semiconductor substrate 11.

According to the second embodiment, the corners 14a and 14b of the recess 14 are used as antifuses. Therefore, electric field concentration occurs particularly at the corners 14a and 14b, and the gate insulating film 18b can be effectively destroyed.

Further, as shown in FIG. 10, the gate electrode 24 may be formed only at one corner 14a, 14b of the recess 14. In this case, not only the above effects can be obtained, but also the area occupied by the antifuse can be further reduced.

When the gate insulating film 18b is formed by, for example, oxidation instead of deposition, the corner portions 14a, 1
In 4b, the thickness of the gate insulating film (oxide film) 18b is smaller than in other flat portions. Therefore, the corner portion 14
The breakdown withstand voltage can be specifically reduced only by a and 14b.

As described above, according to the second embodiment of the present invention, the breakdown voltage of only the antifuse portion of the specific portion (corner portions 14a and 14b) is reduced as compared with the first embodiment. Is possible. Therefore, damage to other transistors is further reduced, and high reliability and improvement in yield of the semiconductor device can be expected.

In the second embodiment of the present invention,
For example, as shown in FIGS. 11 and 12, a recess 14 having a width smaller than that of the recess 14 shown in FIGS. 8 and 9 is formed, and the recess 14 is filled with a gate electrode material (polysilicon film 19) or the like. Good. As shown in FIG. 11, when the polysilicon film 19 is thin, the concave portion 14 is not buried with the polysilicon film 19, so that the insulating film (silicon nitride film 21) serving as the cap film of the gate electrode is buried with the polysilicon film 19. This fills the space of the recess 14 that has not been formed. Further, as shown in FIG. 12, when the polysilicon film 19 is thick, the recess 14 is filled with the polysilicon film 19, and thus the silicon nitride film 21 covers the tungsten film 20 formed outside the recess 14.

Here, the polysilicon film 19 and the silicon nitride film 21 are formed, for example, by LPCVD (Low Pressure Chemica).
Since a film is often formed at a high temperature of several hundred degrees Celsius, for example, by a vapor deposition method, a stress is generated due to a difference in thermal expansion coefficient near a normal temperature at which the semiconductor device is actually used. Therefore, the breakdown voltage of the antifuse portion can be further reduced as compared with the semiconductor devices shown in FIGS. Further, since the gate electrode 24 is drawn out onto the silicon substrate 11, the transistor and the anti-fuse gate electrodes 22 and 24 can be formed at the same height in the lithography process at the time of forming the gate electrodes 22 and 24. . Therefore, the lithography process becomes easy,
Further, the yield is improved. The structure shown in FIG. 12 is different from the structure shown in FIG.
And the tungsten film 20 can be easily positioned.

In the first and second embodiments, the silicon substrate 11 is used as the semiconductor substrate. However, the present invention is not limited to this. For example, as shown in FIG. 13, an SOI (Silicon On Insulator) substrate 31 including an insulating layer 31a and a silicon layer 31b may be used as a semiconductor substrate.

In the first and second embodiments, the silicon oxide film 15 in the recess 14 is completely removed in the step forming step shown in FIG. 3, but the present invention is not limited to this. For example, as shown in FIG. 14, the silicon oxide film 15 may be left in a part of the concave portion 14. In this case, even if the bottom surface of the concave portion 14 is damaged during the RIE of the formation of the concave portion 14, the silicon oxide film 15 is provided on the bottom surface of the concave portion 14 after the formation of the concave portion 14, thereby suppressing the variation in the breakdown voltage of the gate insulating film. it can.

As shown in FIGS. 13 and 14,
By making the width of the groove 14 relatively large, the gate electrode 24
4, a step 24 ′ is formed at the center of the recess 14. Therefore, if this step 24 'is used as an alignment mark portion, it is possible to further reduce the area occupied by the element.

As shown in FIG. 15, a contact plug 28 for connecting to a gate electrode (not shown) of another element may be formed on the element isolation region 16. When a contact hole is formed on the element region, the gate insulating film immediately below the contact hole may be damaged at the time of RIE for forming the contact hole, which may cause a variation in breakdown voltage. However, according to the structure shown in FIG. 15, since the contact hole is formed on the element isolation region 16, it is possible to suppress the variation in the breakdown voltage due to the damage generated when the contact hole is formed.

In the first and second embodiments, the antifuse gate electrode 24 and the recess 14 are in one-to-one correspondence, but the present invention is not limited to this. For example, as shown in FIG. 16, a plurality of recesses 14 may correspond to one gate electrode 24. In this case, the breakdown voltage is stabilized, and the yield of the antifuse is improved. Also,
As shown in FIG. 17, a plurality of gate electrodes 24 may be formed in one recess 14. In this case, the area occupied by the antifuse portion can be further reduced.

[Third Embodiment] In forming a transistor, for example, a CMOS using a polysilicon gate is used.
When a (Complementary MOS) device is considered, N-type or P-type ion implantation is performed for each of a well, a channel region, a gate electrode, a source / drain region, and an LDD (Lightly Doped Drain) region. Therefore, in the third embodiment, the breakdown voltage of the gate insulating film in the antifuse portion is adjusted by using a combination of these steps. Hereinafter, a method for adjusting the breakdown voltage of the gate insulating film in the antifuse portion and a method for reducing the conduction resistance after the breakdown will be described.

As shown in FIG. 18, the conductivity type of the well 32a formed on the surface of the silicon substrate 11 and the conductivity type of the polysilicon film 19a are the same conductivity type (for example, P type).
This makes it possible to reduce the conduction resistance of the antifuse portion after the gate insulating film 18b is broken, and to improve the accuracy of the destruction / non-destruction determination.

As shown in FIG. 19, the conductivity type of the well 32b formed on the surface of the silicon substrate 11 and the conductivity type of the polysilicon film 19b are the same conductivity type (for example, N type).
Further, a P-type LDD region and source / drain regions 33 are formed on the surface of the N well 32b, for example. here,
When the gate insulating film 18b is broken, a positive electric field is applied to the gate electrode 24. In this case, the LDD region and the source
By forming the drain region 33, the electric field concentration at the gate electrode end 24a can be reduced. Therefore, it is possible to reduce the variation in the breakdown voltage due to the electric field concentration at the gate electrode end 24a.

As shown in FIG. 20, the conductivity type of the well 32b formed on the surface of the silicon substrate 11 and the conductivity type of the polysilicon film 19b are the same conductivity type (eg, N type). Impurity concentration of well 32b
Set one or more digits higher. In this device, a positive electric field is applied to the gate electrode 24 when the gate insulating film 18b in the antifuse portion is broken, and a negative electric field is applied to the gate electrode 24 during actual use (determination). As described above, when the sign of the electric field at the time of destruction and that at the time of determination are reversed, the well 32b
Is lower than the impurity concentration of the polysilicon film 19b, the depletion layer formed in the well 32b below the gate at the time of determination becomes thick. Therefore, only a small electric field is effectively applied to the gate insulating film in the antifuse portion that has not been destroyed. Therefore, it is possible to increase the reliability of the determination operation repeatedly performed during actual use.

In each of the above embodiments, a channel impurity may be implanted immediately below the gate electrode 24 in the antifuse portion along with the formation of the transistor. However, as shown in FIG. For example, the P-type semiconductor substrate 34 may be kept at a low impurity concentration without performing ion implantation on the well and the channel region. In this apparatus, a negative electric field is applied to the gate electrode 24 when the gate insulating film 18b in the antifuse portion is destroyed, and a positive electric field is applied to the gate electrode 24 when making a determination.
In this case, the same effect as in FIG. 20 can be obtained.
Furthermore, since the thickness of the depletion layer is further increased due to the very low impurity concentration initially included in the semiconductor substrate 34 itself, it is possible to further improve the reliability of the determination operation in actual use.

The gate insulating film 1 in the antifuse portion
The method of adjusting the breakdown voltage of 8b is not limited to the above embodiment.

For example, the breakdown voltage of the antifuse can be adjusted by adjusting the amount of damage to the bottom, side, and corner of the recess 14. In other words, for example, if the breakdown voltage is too low below a desired value, and if this is due to damage caused by RIE, the RI
It is possible to reduce the amount of damage by lowering the ion energy at E. Thereby, the breakdown voltage can be recovered to some extent.

When the silicon oxide film 15 is removed in the step forming step shown in FIG.
By etching the surface of the silicon substrate 11 thinly by isotropic etching such as an ical dry etching method, a damaged layer on the outermost surface of the silicon substrate 11 can be removed. Further, it is also possible to make the corners 14a and 14b of the recess 14 rounded to reduce the effect of electric field concentration. Even with these methods, it is possible to recover the breakdown voltage, which has fallen below a desired value, to some extent.

On the other hand, when it is desired to further reduce the breakdown voltage, a high-power RIE is used instead of the wet etching method when removing the silicon oxide film 15 in the step forming step.
By using the method, it is possible to further introduce damage to the bottom surface of the concave portion 14.

Further, the silicon oxide film 15
After removing the resist film 17 and before removing the resist film 17, impurity ions are introduced using an ion implantation technique. Thereby, it is possible to adjust the thickness of the gate oxide film 18 formed thereafter. Therefore,
The breakdown voltage of the gate insulating film 18b can be adjusted. For example, after a lithography process for providing a step, implantation of nitrogen ions is performed. As a result, the gate oxide film 18 to be formed later can be formed specifically thin, and a desired breakdown voltage can be obtained by using the gate oxide film 18 as an antifuse. In this case, it is not always necessary to provide a step in the antifuse portion, but by providing the step, the breakdown voltage can be reduced more effectively.

[Fourth Embodiment] The fourth embodiment is a plan view of the semiconductor device according to the first to third embodiments. It should be noted that FIGS.
14A, reference numeral 14c indicates a mask.

FIG. 22 (a) shows a plurality of antifuse gate electrodes 2 in one recess 14 as shown in FIG.
4 shows a top view when 4 is formed. FIG. 22 (b)
FIG. 23 shows a cross-sectional view along the line 22b-22b in FIG. In this case, the gate electrode 24 is formed in the recess 14 in an island shape.

FIG. 23A shows that, as shown in FIG. 15, the recess 14 is filled with the gate electrode 24 for antifuse, and the contact plug 28 is formed on the element isolation region 16.
FIG. 4 shows a top view in the case where is formed. FIG. 23B is a sectional view taken along line 23b-23b in FIG.

FIG. 24A is a top view when the corner portions 14a and 14b of the concave portion 14 are actively used as shown in FIGS. FIG. 24 (b)
FIG. 25 shows a sectional view taken along the line 24b-24b in FIG.

FIG. 25A is a top view showing a case where an acute angle portion 14d is formed in the concave portion 14 in order to further concentrate the electric field. FIG. 25 (b) is a view similar to 25b in FIG. 25 (a).
FIG. 4 shows a cross-sectional view along line −25b.

According to the fourth embodiment, the antifuse portion of the present invention can be formed with the minimum processing size of the element region 16a and the gate electrode 24 or a multiple of the minimum processing size (for example, 0.13 μm generation). About 0.4 μm × 1 μm). For this reason, the area occupied by the antifuse portion is the same as that of a conventional antifuse portion (for example, about 2 μm × 10 μm).
Can be made much smaller than. Therefore, the chip area of the semiconductor device can be reduced and the manufacturing cost can be reduced.

[Fifth Embodiment] Generally, as shown in FIG. 26, a capacitor element for stabilizing a power supply is often prepared inside a semiconductor device, and is composed of a gate insulating film 48. A capacitor is used. In order to supply a more stable power supply, it is necessary to form a capacitor having a larger capacitance in the semiconductor device.
However, in recent years, the area occupied by the capacitor for stabilizing the power supply has occupied a large proportion of the area of the entire chip, and this is becoming a factor that increases the manufacturing cost. Therefore, a reduction in the area occupied by the power-stabilized capacitor has been required.

Thus, in the fifth embodiment, an example is shown in which the structure of a semiconductor device having a plurality of recesses 14 as shown in FIG. 16 is applied to a capacitor element.

As shown in FIG. 27A, similarly to the structure of FIG. 16, a plurality of recesses 14 are formed in the silicon substrate 11, and the recesses 14 are filled with the gate insulating film 18b 'and the polysilicon film 19. Have been.

Here, as the gate insulating film 18b 'for the capacitor element, for example, a silicon oxynitride film is preferably used. This silicon oxynitride film is formed, for example, by oxidizing the surface of the silicon substrate 11 in a nitrogen / steam / hydrochloric acid atmosphere at 750 ° C. and then performing nitridation in a nitrogen / nitrogen monoxide atmosphere at 900 ° C. It has been found that when this silicon oxynitride film is used, the breakdown voltage at the corners of the recess 14 and at the bottom and side surfaces of the recess 14 is not easily reduced. Therefore, as described in the first to fourth embodiments, the step surface (recess 14) of the silicon substrate 11 is used.
Can be used not as an antifuse element but as a capacitor element for stabilizing a power supply.

According to the fifth embodiment, since the silicon oxynitride film whose breakdown withstand voltage is hardly reduced is used as the gate insulating film 18b ', the concave portion 14 of the silicon substrate 11 is not used as an antifuse element but for stabilizing the power supply. Can be used as a capacitor element. Then, by forming a plurality of recesses 14 in the silicon substrate 11, the surface area of the gate insulating film 18b 'can be increased.
Therefore, the capacity of the capacitor can be increased without increasing the area occupied by the capacitor.

For example, when the silicon substrate 11 has a width of 0.1
When the concave portion 14 having a depth of 3 μm and a depth of 0.2 μm is repeatedly formed with a space of 0.13 μm, even if the same gate insulating film is used, the area of the capacitor element is reduced by one area as compared with the conventional case.
/2.5. Therefore, the area occupied by the capacitor can be reduced, and a more inexpensive semiconductor device can be provided.

Note that, as shown in FIG.
The shape of 4 is preferably a line shape, not an island shape as shown in FIG. Thus, the surface area of the gate insulating film 18b 'can be increased as much as possible, so that the capacitance of the capacitor can be increased without increasing the area occupied by the capacitor.

In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[0086]

As described above, according to the present invention, a gate insulating film having a desired breakdown voltage can be obtained without increasing the number of manufacturing steps by applying the step for aligning marks to the formation of an antifuse. And a method for manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 1;

FIG. 3 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 2;

FIG. 4 is a sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 3;

FIG. 5 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 4;

FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention, following FIG. 5;

FIG. 7 is a sectional view showing the manufacturing process of the semiconductor device according to another first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing an antifuse portion using a corner portion of a concave portion according to the second embodiment of the present invention.

FIG. 9 is a cross-sectional view showing another antifuse portion using a corner portion of a concave portion according to the second embodiment of the present invention.

FIG. 10 is a cross-sectional view showing an antifuse portion using a corner portion on one side of a concave portion according to the second embodiment of the present invention.

FIG. 11 is a cross-sectional view showing an antifuse portion according to a second embodiment of the present invention when a concave portion is buried.

FIG. 12 is a cross-sectional view showing another antifuse portion according to the second embodiment of the present invention when a concave portion is buried with a polysilicon film.

FIG. 13 relates to the first and second embodiments of the present invention,
FIG. 4 is a cross-sectional view illustrating an antifuse portion when an OI substrate is used.

FIG. 14 is a cross-sectional view showing an antifuse portion according to the first and second embodiments of the present invention when a silicon oxide film is buried halfway into a concave portion.

FIG. 15 is a cross-sectional view showing an antifuse portion when a contact is formed on an element isolation region according to the first and second embodiments of the present invention.

FIG. 16 is a sectional view showing a case where a plurality of recesses correspond to one antifuse portion according to the first and second embodiments of the present invention.

FIG. 17 is a cross-sectional view showing a case where one recess corresponds to a plurality of antifuse portions according to the first and second embodiments of the present invention.

FIG. 18 is a sectional view showing an antifuse portion according to the third embodiment of the present invention, in which the impurity concentration of the gate is higher than that of the well.

FIG. 19 is a sectional view showing an antifuse portion according to a third embodiment of the present invention, in which the impurity concentration of the gate is higher than that of the well and the LDD region is formed.

FIG. 20 is a sectional view showing an antifuse portion according to the third embodiment of the present invention, in which the impurity concentration of the gate is higher than that of the well.

FIG. 21 is a sectional view showing an antifuse portion according to the third embodiment of the present invention, in which the impurity concentration of the gate is higher than that of the well.

22 (a) is a top view showing a case where a plurality of antifuse gate electrodes are formed in one recess, and FIG. 22 (b) is a line 22b-22b in FIG. 22 (a). Sectional view along.

FIG. 23A is a top view showing a case where a concave portion is filled with a gate electrode for antifuse and a contact is formed on an element isolation region. FIG. 23B is a top view showing FIG.
Sectional drawing which followed the 23b-23b line of 3 (a).

24A is a top view showing a case where corner portions of a concave portion are actively used, and FIG.
Sectional drawing which followed the 24b-24b line of (a).

FIG. 25 (a) is a top view showing a case where an acute angle portion is formed in a concave portion, and FIG. 25 (b) is a view 25 in FIG. 25 (a).
Sectional drawing along the b-25b line.

FIG. 26 is a sectional view of a semiconductor device having a capacitor element according to a conventional technique.

FIG. 27A is a cross-sectional view of a semiconductor device having a capacitor element according to a fifth embodiment of the present invention,
FIG. 27B is a top view of the recess shown in FIG.

FIG. 28 is a sectional view showing a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 29 is a cross-sectional view showing a manufacturing step of the conventional semiconductor device, following FIG. 28;

FIG. 30 is a sectional view showing a manufacturing step of the semiconductor device according to the conventional technique, following FIG. 29;

FIG. 31 is a sectional view showing a manufacturing step of a conventional semiconductor device, following FIG. 30;

FIG. 32 is a sectional view showing a manufacturing step of the semiconductor device according to the related art, following FIG. 31;

FIG. 33 is a sectional view showing a manufacturing step of a conventional semiconductor device, following FIG. 32;

[Explanation of symbols]

11: Silicon substrate, 12: First concave portion for element isolation region, 13: Second concave portion for antifuse portion, 14: Third concave portion for alignment mark portion, 14a, 14b: Corner portion, 14c ... Mask, 14d: acute angle portion, 15: silicon oxide film, 16: element isolation region, 17: resist, 18, 18a, 18b: gate insulating film, 18b ': gate insulating film for capacitor element, 19: polysilicon film, 19a: P ⁺ type polysilicon film, 19b: N ⁺ type polysilicon film, 20: tungsten film, 21: silicon nitride film, 22: first gate electrode for transistor, 23: alignment mark portion, 24: antifuse Second gate electrode, 24a: gate electrode end, 24 ': step, 25: gate side wall, 26: source / drain region, 27, 30 ... interlayer Enmaku, 28 ... contact plug, 29 ... upper wiring, 32a ... P-well, 32 b ... N-well, 33 ... LDD regions and source and drain regions, 34 ... P-type semiconductor substrate.

Claims (20)

[Claims] A concave portion formed in the semiconductor substrate; a first gate insulating film selectively formed on the semiconductor substrate; and a second gate insulating film formed on at least a bottom surface of the concave portion. A semiconductor device, comprising: a first conductive film formed on the first gate insulating film; and a second conductive film formed on the second gate insulating film. 2. The first conductive film, wherein the second gate insulating film and the second conductive film are formed on a bottom surface of the concave portion, on both side surfaces or one side surface of the concave portion, and on the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the film surface of the first conductive film and the film surface of the second conductive film on the semiconductor substrate have the same height. 3. The semiconductor device according to claim 1, wherein said second gate insulating film is formed at a corner of said recess. 4. An insulating film is formed on the second conductive film, and the concave portion is filled with the insulating film, the second gate insulating film, and the second conductive film. The semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein the concave portion is filled with the second gate insulating film and the second conductive film, and a film surface of the second conductive film is substantially flat. Semiconductor device. 6. The semiconductor device according to claim 1, wherein said semiconductor substrate is an SOI substrate. 7. An element isolation region formed in said semiconductor substrate, and said second gate insulating film and said second conductive film are drawn out to above said element isolation region. The semiconductor device according to claim 1, further comprising: a contact electrically connected to the conductive film, and a wiring electrically connected to the contact. 8. A plurality of recesses are formed, and the plurality of recesses are filled with the second gate insulating film and the second conductive film. The film surface of the second conductive film is substantially flat. The semiconductor device according to claim 1, wherein: 9. The semiconductor device according to claim 1, wherein a plurality of gate electrodes made of the second conductive film are formed in the recess. 10. The semiconductor device according to claim 1, wherein an impurity concentration of said second conductive film is higher than an impurity concentration of said semiconductor substrate. 11. The semiconductor device according to claim 1, wherein said second insulating film is an insulating film for an antifuse portion or a capacitor element. 12. A step of forming first, second, and third concave portions in a semiconductor substrate; filling the first, second, and third concave portions with an insulating film; Forming a device isolation region in the first recess by flattening the surface of the insulating film until the insulating film is exposed; and removing the insulating film in the second and third recesses Forming a registration mark portion in the second concave portion, forming a gate insulating film over the entire surface, forming a conductive film on the gate insulating film, and selecting the conductive film. Forming a first gate electrode on the semiconductor substrate, and forming a second gate electrode in a third concave portion. 13. The manufacturing of a semiconductor device according to claim 12, wherein a gate insulating film is formed on the entire surface while a part of the insulating film formed in the third recess remains. Method. 14. The semiconductor device according to claim 12, wherein the second gate electrode is formed on a bottom surface of the third recess, both side surfaces or one side surface of the third recess, and on the semiconductor substrate. The manufacturing method of the semiconductor device described in the above. 15. The method according to claim 12, wherein the second gate electrode is formed so as to fill the third recess. 16. The semiconductor device according to claim 16, wherein the second gate electrode is formed so as to extend from inside the third recess to above the element isolation region.
13. The method according to claim 12, wherein a contact is formed on the second gate electrode on the element isolation region. 17. The method according to claim 12, wherein a plurality of the third recesses are formed. 18. The semiconductor device according to claim 12, wherein a plurality of the second gate electrodes are formed in the third recess.
The manufacturing method of the semiconductor device described in the above. 19. The semiconductor device according to claim 1, wherein an impurity concentration of the conductive film is higher than an impurity concentration of the semiconductor substrate.
3. The method for manufacturing a semiconductor device according to item 2. 20. The method according to claim 12, wherein the second gate electrode is a gate electrode for an antifuse portion or a capacitor element.