JP6805510B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP6805510B2 JP6805510B2 JP2016049339A JP2016049339A JP6805510B2 JP 6805510 B2 JP6805510 B2 JP 6805510B2 JP 2016049339 A JP2016049339 A JP 2016049339A JP 2016049339 A JP2016049339 A JP 2016049339A JP 6805510 B2 JP6805510 B2 JP 6805510B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
本発明の第1の実施形態について図を参照して詳細に説明する。図1は、本実施形態の半導体装置の構成の概要を示したものである。本実施形態の半導体装置は、配線基板1と、半導体素子2と、第1の封止層3と、第2の封止層4を備えている。配線基板1は、信号配線を有する。半導体素子2は、配線基板1上に固定され、所定の回路パターンを有する。第1の封止層3は、半導体素子2が固定されている領域を含む第1の領域を全て覆うように第1の樹脂によって配線基板上に形成されている。第2の封止層4は、第1の封止層3上の第1の領域より狭い第2の領域に、第1の樹脂よりも粘度が高い第2の樹脂によって形成されている。
本発明の第2の実施形態について図を参照して詳細に説明する。図2は、本実施形態の半導体装置の構成の概要を示した断面図である。また、図3は、本実施形態の半導体装置を上方向から見た際の構成を示す平面図である。
2 半導体素子
3 第1の封止層
4 第2の封止層
11 配線基板
12 金属ワイヤ
13 半導体素子
14 第1の封止樹脂
15 第2の封止樹脂
16 信号配線
17 固着層
18 第3の封止樹脂
20 塗布可能領域
Claims (8)
- 信号配線を有する配線基板と、
前記配線基板上に固定され、所定の回路パターンを有する半導体素子と、
前記半導体素子が固定されている領域を含む第1の領域を全て覆うように第1の樹脂によって前記配線基板上に形成された第1の封止層と、
前記第1の封止層上の前記第1の領域より狭い第2の領域に、前記第1の樹脂よりも粘度が高い第2の樹脂によって形成された第2の封止層と、
前記第2の封止層上に、前記第1の領域より狭い第3の領域に形成された第3の封止層と
を備えることを特徴とする半導体装置。 - 前記信号配線と前記所定の回路パターンを電気的に接続するワイヤをさらに備え、
前記第1の領域は、前記ワイヤが前記配線基板と接続されている領域をさらに含み、
前記第1の封止層は、前記半導体素子および前記ワイヤを全て覆う高さまで形成されていることを特徴とする請求項1に記載の半導体装置。 - 前記第2の樹脂は、前記第1の樹脂よりも所定の充填物の含有量が多いことを特徴とする請求項1または2に記載の半導体装置。
- 前記第2の封止層は、前記半導体素子の面積よりも大きい前記第2の領域に、前記半導体素子の上方を覆うように形成されていることを特徴とする請求項1から3いずれかに記載の半導体装置。
- 前記第1の封止層と前記第2の封止層の間に、前記第1の樹脂の層と前記第2の樹脂の層の界面が形成されていることを特徴とする請求項1から4いずれかに記載の半導体装置。
- 信号配線を有し、所定の回路パターンを有する半導体素子が上面に固定された配線基板の前記上面に、
前記半導体素子が固定されている領域を含む第1の領域を全て覆うように、流動性を有する第1の樹脂を供給し、
前記第1の樹脂を硬化させて第1の封止層を形成し、
前記第1の封止層上の前記第1の領域より狭い第2の領域に、前記第1の樹脂よりも粘度が高い第2の樹脂によって第2の封止層を形成し、
前記第2の封止層上において、前記第1の領域より狭い第3の領域に第3の封止層を形成することを特徴とする半導体装置の製造方法。 - 前記第1の領域は、前記信号配線と前記所定の回路パターンを電気的に接続するワイヤが前記配線基板と接続されている領域をさらに含み、
前記第1の封止層を、前記半導体素子と前記ワイヤを全て覆う高さまで形成することを特徴とする請求項6に記載の半導体装置の製造方法。 - 前記第1の樹脂が完全に硬化していない状態で、前記第1の封止層の上に前記第2の樹脂を塗布して、前記第1の樹脂と前記第2の樹脂を同時に硬化させることを特徴とする請求項6または7に記載の半導体装置の製造方法。
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JP2000100997A (ja) * | 1998-09-17 | 2000-04-07 | Mitsubishi Electric Corp | 樹脂封止型半導体装置およびその樹脂封止方法 |
JP2001077133A (ja) * | 1999-09-06 | 2001-03-23 | Hitachi Ltd | 半導体装置およびその製造方法 |
US7723162B2 (en) * | 2002-03-22 | 2010-05-25 | White Electronic Designs Corporation | Method for producing shock and tamper resistant microelectronic devices |
JP2005235944A (ja) * | 2004-02-18 | 2005-09-02 | Tdk Corp | 電子デバイスおよびその製造方法 |
JP2008235669A (ja) * | 2007-03-22 | 2008-10-02 | Shin Etsu Chem Co Ltd | 半導体装置及びその製造方法 |
JP5877291B2 (ja) * | 2010-05-14 | 2016-03-08 | パナソニックIpマネジメント株式会社 | 半導体装置およびその製造方法 |
KR101711479B1 (ko) * | 2010-10-06 | 2017-03-03 | 삼성전자 주식회사 | 반도체 패키지 장치 및 그의 검사 시스템 |
JP5570476B2 (ja) * | 2011-07-05 | 2014-08-13 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP5998033B2 (ja) * | 2012-12-07 | 2016-09-28 | 株式会社ジェイデバイス | 半導体装置及びその製造方法 |
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