JP5877291B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP5877291B2 JP5877291B2 JP2010112023A JP2010112023A JP5877291B2 JP 5877291 B2 JP5877291 B2 JP 5877291B2 JP 2010112023 A JP2010112023 A JP 2010112023A JP 2010112023 A JP2010112023 A JP 2010112023A JP 5877291 B2 JP5877291 B2 JP 5877291B2
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- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- semiconductor element
- circuit board
- thermal expansion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
2 半導体素子
3 突起電極
4 樹脂回路基板
5 第1の樹脂
6 第2の樹脂
7 凹部
8 第3の樹脂または金属
9 フリップチップ実装された樹脂回路基板
10 第2の樹脂により封止樹脂が形成された樹脂回路基板
11,15 回転ブレード
12 封止樹脂に凹部を形成した樹脂回路基板
13 ディスペンサ
14 第3の樹脂により封止樹脂が形成された樹脂回路基板
Claims (4)
- 突起電極が形成された半導体素子と、
前記半導体素子が前記突起電極を介して実装された回路基板と、
前記半導体素子と前記回路基板間の隙間を封止する第1の樹脂と、
前記半導体素子の実装面と対向する上面を覆い、かつ前記半導体素子の上部に凹部が形成される第2の樹脂とを備え、
第3の樹脂が前記凹部に設けられ、
前記第2の樹脂の熱膨張係数が、前記回路基板の熱膨張係数よりも大きく、かつ前記第1の樹脂の熱膨張係数より小さく、前記第3の樹脂の熱膨張係数が前記第2の樹脂の熱膨張係数よりも小さいことを特徴とする半導体装置。 - 前記凹部が少なくとも1本の直線状の溝によって形成され、前記直線状の溝の幅が前記半導体素子の短辺の幅より小さいことを特徴とする請求項1に記載の半導体装置。
- 複数本の前記溝が、前記半導体素子の中心上で交差することを特徴とする請求項2に記載の半導体装置。
- 回路基板の一主面に第1の樹脂を塗布する工程と、
前記第1の樹脂を介して前記回路基板の一主面上に複数の半導体素子を実装する工程と、実装した前記複数の半導体素子を第2の樹脂で封止する工程と、
前記第2の樹脂における前記半導体素子の上部に凹部を形成する工程と、
前記凹部に第3の樹脂を塗布する工程と、
前記半導体素子が少なくとも1個含まれるように前記回路基板を分割して、それぞれを半導体装置とする工程とを有し、
前記第2の樹脂の熱膨張係数が、前記回路基板の熱膨張係数よりも大きく、かつ前記第1の樹脂の熱膨張係数より小さく、前記第3の樹脂の熱膨張係数が前記第2の樹脂の熱膨張係数よりも小さいことを特徴とする半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010112023A JP5877291B2 (ja) | 2010-05-14 | 2010-05-14 | 半導体装置およびその製造方法 |
Applications Claiming Priority (1)
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---|---|---|---|
JP2010112023A JP5877291B2 (ja) | 2010-05-14 | 2010-05-14 | 半導体装置およびその製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2011243624A JP2011243624A (ja) | 2011-12-01 |
JP2011243624A5 JP2011243624A5 (ja) | 2013-05-02 |
JP5877291B2 true JP5877291B2 (ja) | 2016-03-08 |
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JP2010112023A Expired - Fee Related JP5877291B2 (ja) | 2010-05-14 | 2010-05-14 | 半導体装置およびその製造方法 |
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Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2012165111A1 (ja) * | 2011-05-31 | 2012-12-06 | 株式会社村田製作所 | 多層基板の製造方法および多層基板 |
JP6051630B2 (ja) * | 2011-07-13 | 2016-12-27 | 味の素株式会社 | 半導体パッケージ |
JP6805510B2 (ja) * | 2016-03-14 | 2020-12-23 | 日本電気株式会社 | 半導体装置およびその製造方法 |
KR102015335B1 (ko) | 2016-03-15 | 2019-08-28 | 삼성전자주식회사 | 전자부품 패키지 및 그 제조방법 |
JP6897056B2 (ja) | 2016-10-20 | 2021-06-30 | 富士電機株式会社 | 半導体装置及び半導体装置製造方法 |
JP6968553B2 (ja) | 2017-03-09 | 2021-11-17 | キヤノン株式会社 | 電子部品及びその製造方法 |
JP6984155B2 (ja) * | 2017-04-06 | 2021-12-17 | 株式会社デンソー | 電子装置 |
JP2018207212A (ja) * | 2017-05-31 | 2018-12-27 | 京セラ株式会社 | 水晶デバイス |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH05291434A (ja) * | 1992-04-13 | 1993-11-05 | Mitsubishi Electric Corp | 樹脂封止半導体装置およびその製造方法 |
JP3443313B2 (ja) * | 1998-03-26 | 2003-09-02 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
JP2001127212A (ja) * | 1999-10-26 | 2001-05-11 | Hitachi Ltd | 半導体装置および半導体装置の製造方法 |
JP4328520B2 (ja) * | 2002-12-06 | 2009-09-09 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JP2007066960A (ja) * | 2005-08-29 | 2007-03-15 | Seiko Instruments Inc | 半導体パッケージ及び回路基板並びに半導体パッケージの製造方法 |
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- 2010-05-14 JP JP2010112023A patent/JP5877291B2/ja not_active Expired - Fee Related
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JP2011243624A (ja) | 2011-12-01 |
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