JP6772995B2 - Soiウェーハの製造方法およびsoiウェーハ - Google Patents

Soiウェーハの製造方法およびsoiウェーハ Download PDF

Info

Publication number
JP6772995B2
JP6772995B2 JP2017183912A JP2017183912A JP6772995B2 JP 6772995 B2 JP6772995 B2 JP 6772995B2 JP 2017183912 A JP2017183912 A JP 2017183912A JP 2017183912 A JP2017183912 A JP 2017183912A JP 6772995 B2 JP6772995 B2 JP 6772995B2
Authority
JP
Japan
Prior art keywords
diamond
support substrate
layer
soi wafer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2017183912A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019062020A (ja
Inventor
祥泰 古賀
祥泰 古賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Corp
Original Assignee
Sumco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Corp filed Critical Sumco Corp
Priority to JP2017183912A priority Critical patent/JP6772995B2/ja
Priority to FR1858146A priority patent/FR3071663B1/fr
Publication of JP2019062020A publication Critical patent/JP2019062020A/ja
Application granted granted Critical
Publication of JP6772995B2 publication Critical patent/JP6772995B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02441Group 14 semiconducting materials
    • H01L21/02444Carbon, e.g. diamond-like carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02527Carbon, e.g. diamond-like carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02623Liquid deposition
    • H01L21/02628Liquid deposition using solutions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02658Pretreatments

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)
  • Recrystallisation Techniques (AREA)
JP2017183912A 2017-09-25 2017-09-25 Soiウェーハの製造方法およびsoiウェーハ Active JP6772995B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2017183912A JP6772995B2 (ja) 2017-09-25 2017-09-25 Soiウェーハの製造方法およびsoiウェーハ
FR1858146A FR3071663B1 (fr) 2017-09-25 2018-09-11 Procede de fabrication de plaque soi, et plaque soi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017183912A JP6772995B2 (ja) 2017-09-25 2017-09-25 Soiウェーハの製造方法およびsoiウェーハ

Publications (2)

Publication Number Publication Date
JP2019062020A JP2019062020A (ja) 2019-04-18
JP6772995B2 true JP6772995B2 (ja) 2020-10-21

Family

ID=65858443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017183912A Active JP6772995B2 (ja) 2017-09-25 2017-09-25 Soiウェーハの製造方法およびsoiウェーハ

Country Status (2)

Country Link
JP (1) JP6772995B2 (fr)
FR (1) FR3071663B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3967792A4 (fr) * 2019-05-10 2023-05-17 National Institute Of Advanced Industrial Science And Technology Corps composite comprenant un corps de cristal de diamant

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01138198A (ja) * 1987-11-26 1989-05-31 Nec Corp ダイヤモンド膜の製造方法
JPH02206118A (ja) * 1989-02-06 1990-08-15 Hitachi Ltd 半導体素子
JPH09263488A (ja) * 1996-03-27 1997-10-07 Matsushita Electric Ind Co Ltd ダイヤモンド膜の製造方法
JP3951324B2 (ja) * 1996-09-03 2007-08-01 住友電気工業株式会社 気相合成ダイヤモンドおよびその製造方法
JP4654389B2 (ja) * 2006-01-16 2011-03-16 株式会社ムサシノエンジニアリング ダイヤモンドヒートスプレッダの常温接合方法,及び半導体デバイスの放熱部
JP2010258083A (ja) * 2009-04-22 2010-11-11 Panasonic Corp Soiウェーハ、その製造方法および半導体装置の製造方法
KR101985526B1 (ko) * 2011-01-31 2019-06-03 다다또모 스가 접합 기판 제작 방법, 접합 기판, 기판 접합 방법, 접합 기판 제작 장치 및 기판 접합체
JP6248458B2 (ja) * 2013-08-05 2017-12-20 株式会社Sumco 貼り合わせウェーハの製造方法および貼り合わせウェーハ

Also Published As

Publication number Publication date
FR3071663B1 (fr) 2022-02-18
JP2019062020A (ja) 2019-04-18
FR3071663A1 (fr) 2019-03-29

Similar Documents

Publication Publication Date Title
JP7115297B2 (ja) 多結晶ダイヤモンド自立基板及びその製造方法
JPH09223782A (ja) Soi基板の製造方法
JPH11307472A (ja) 水素イオン剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ
TW200913128A (en) Method for manufacturing SOI wafer
JP2001274368A (ja) 貼り合わせウエーハの製造方法およびこの方法で製造された貼り合わせウエーハ
JPWO2014017369A1 (ja) ハイブリッド基板の製造方法及びハイブリッド基板
TWI355711B (en) Method of producing simox wafer
TW201133615A (en) Wafer adhesion method
JP2009253237A (ja) 貼り合わせウェーハの製造方法
TWI609434B (zh) SOS substrate manufacturing method and SOS substrate
JP6772995B2 (ja) Soiウェーハの製造方法およびsoiウェーハ
JP7172556B2 (ja) 多結晶ダイヤモンド自立基板の製造方法
JP6614066B2 (ja) シリコン接合ウェーハの製造方法
JP7480699B2 (ja) 多結晶ダイヤモンド自立基板を用いた積層基板及びその製造方法
JP7024668B2 (ja) Soiウェーハ及びその製造方法
JP2018064057A (ja) シリコン接合ウェーハの製造方法およびシリコン接合ウェーハ
JP6825509B2 (ja) ダイヤモンド積層シリコンウェーハの製造方法およびダイヤモンド積層シリコンウェーハ
TWI643250B (zh) Method for manufacturing epitaxial wafer and epitaxial wafer
JP2023085098A (ja) 積層ウェーハ及びその製造方法
JP2010129839A (ja) 貼り合わせウェーハの製造方法
JP2009289948A (ja) 貼り合わせウェーハの製造方法
JP7238753B2 (ja) 接合ウェーハ及びその製造方法
JP2019110225A (ja) 貼合せウェーハの製造方法および貼合せウェーハ
JP5364345B2 (ja) Soi基板の作製方法
JP2009111347A (ja) 貼り合わせウェーハの製造方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190925

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200825

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200901

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200914

R150 Certificate of patent or registration of utility model

Ref document number: 6772995

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250