FR3071663B1 - Procede de fabrication de plaque soi, et plaque soi - Google Patents

Procede de fabrication de plaque soi, et plaque soi Download PDF

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Publication number
FR3071663B1
FR3071663B1 FR1858146A FR1858146A FR3071663B1 FR 3071663 B1 FR3071663 B1 FR 3071663B1 FR 1858146 A FR1858146 A FR 1858146A FR 1858146 A FR1858146 A FR 1858146A FR 3071663 B1 FR3071663 B1 FR 3071663B1
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France
Prior art keywords
soi wafer
manufacturing
active layer
support substrate
diamond particles
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1858146A
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English (en)
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FR3071663A1 (fr
Inventor
Yoshihiro Koga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Corp
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Sumco Corp
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Publication date
Application filed by Sumco Corp filed Critical Sumco Corp
Publication of FR3071663A1 publication Critical patent/FR3071663A1/fr
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Publication of FR3071663B1 publication Critical patent/FR3071663B1/fr
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/02444—Carbon, e.g. diamond-like carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02527—Carbon, e.g. diamond-like carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02623—Liquid deposition
    • H01L21/02628—Liquid deposition using solutions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Plasma & Fusion (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne un procédé de fabrication d'une plaque SOI, grâce auquel une plaque SOI présentant de bonnes propriétés de rayonnement thermique peut être fabriquée par collage sous vide à température normale. Le procédé de fabrication d'une plaque SOI (100) comprend les étapes suivantes : appliquer des particules de diamant (14) sur une surface d'un substrat de support (10) constitué d'un monocristal de silicium, puis former par croissance une couche de diamant (16) par dépôt chimique en phase vapeur en utilisant les particules de diamant (14) en tant que noyaux sur le substrat de support (10), les particules de diamant formées ayant une taille de particule maximale égale ou inférieure à 2,0 μm ; aplanir la surface (16A) de la couche de diamant ; coller ensemble le substrat de support (10) et un substrat de couche active (20) constitué d'un monocristal de silicium par collage sous vide à température normale ; et réduire l'épaisseur du substrat de couche active (20). Ainsi, une plaque SOI possédant une couche active (24) est obtenue.
FR1858146A 2017-09-25 2018-09-11 Procede de fabrication de plaque soi, et plaque soi Active FR3071663B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017183912A JP6772995B2 (ja) 2017-09-25 2017-09-25 Ｓｏｉウェーハの製造方法およびｓｏｉウェーハ
JP2017183912 2017-09-25

Publications (2)

Publication Number Publication Date
FR3071663A1 FR3071663A1 (fr) 2019-03-29
FR3071663B1 true FR3071663B1 (fr) 2022-02-18

Family

ID=65858443

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1858146A Active FR3071663B1 (fr) 2017-09-25 2018-09-11 Procede de fabrication de plaque soi, et plaque soi

Country Status (2)

Country Link
JP (1) JP6772995B2 (fr)
FR (1) FR3071663B1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12027440B2 (en) 2019-05-10 2024-07-02 National Institute Of Advanced Industrial Science And Technology Composite having diamond crystal base
JP7600973B2 (ja) 2021-12-08 2024-12-17 株式会社Sumco 積層ウェーハ及びその製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01138198A (ja) * 1987-11-26 1989-05-31 Nec Corp ダイヤモンド膜の製造方法
JPH02206118A (ja) * 1989-02-06 1990-08-15 Hitachi Ltd 半導体素子
JPH09263488A (ja) * 1996-03-27 1997-10-07 Matsushita Electric Ind Co Ltd ダイヤモンド膜の製造方法
JP3951324B2 (ja) * 1996-09-03 2007-08-01 住友電気工業株式会社 気相合成ダイヤモンドおよびその製造方法
JP4654389B2 (ja) * 2006-01-16 2011-03-16 株式会社ムサシノエンジニアリング ダイヤモンドヒートスプレッダの常温接合方法，及び半導体デバイスの放熱部
JP2010258083A (ja) * 2009-04-22 2010-11-11 Panasonic Corp Ｓｏｉウェーハ、その製造方法および半導体装置の製造方法
WO2012105473A1 (fr) * 2011-01-31 2012-08-09 ボンドテック株式会社 Procédé de fabrication de substrat lié, substrat lié, procédé de liaison de substrat, dispositif de fabrication de substrat lié et ensemble substrat
JP6248458B2 (ja) * 2013-08-05 2017-12-20 株式会社Sumco 貼り合わせウェーハの製造方法および貼り合わせウェーハ

Also Published As

Publication number Publication date
JP2019062020A (ja) 2019-04-18
FR3071663A1 (fr) 2019-03-29
JP6772995B2 (ja) 2020-10-21

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