JP6759626B2 - エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ - Google Patents

エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ Download PDF

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Publication number
JP6759626B2
JP6759626B2 JP2016034448A JP2016034448A JP6759626B2 JP 6759626 B2 JP6759626 B2 JP 6759626B2 JP 2016034448 A JP2016034448 A JP 2016034448A JP 2016034448 A JP2016034448 A JP 2016034448A JP 6759626 B2 JP6759626 B2 JP 6759626B2
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Prior art keywords
layer
wafer
epitaxial
silicon
support substrate
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JP2016034448A
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English (en)
Japanese (ja)
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JP2017152570A (ja
Inventor
祥泰 古賀
祥泰 古賀
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Sumco Corp
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Sumco Corp
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Application filed by Sumco Corp filed Critical Sumco Corp
Priority to JP2016034448A priority Critical patent/JP6759626B2/ja
Priority to CN201680081475.5A priority patent/CN108885998B/zh
Priority to KR1020187016525A priority patent/KR102129190B1/ko
Priority to PCT/JP2016/085046 priority patent/WO2017145470A1/ja
Priority to TW105141145A priority patent/TWI643250B/zh
Publication of JP2017152570A publication Critical patent/JP2017152570A/ja
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Publication of JP6759626B2 publication Critical patent/JP6759626B2/ja
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02293Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Plasma & Fusion (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Recrystallisation Techniques (AREA)
JP2016034448A 2016-02-25 2016-02-25 エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ Active JP6759626B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2016034448A JP6759626B2 (ja) 2016-02-25 2016-02-25 エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ
CN201680081475.5A CN108885998B (zh) 2016-02-25 2016-11-25 外延晶圆的制造方法及外延晶圆
KR1020187016525A KR102129190B1 (ko) 2016-02-25 2016-11-25 에피택셜 웨이퍼의 제조 방법 및 에피택셜 웨이퍼
PCT/JP2016/085046 WO2017145470A1 (ja) 2016-02-25 2016-11-25 エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ
TW105141145A TWI643250B (zh) 2016-02-25 2016-12-13 Method for manufacturing epitaxial wafer and epitaxial wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016034448A JP6759626B2 (ja) 2016-02-25 2016-02-25 エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ

Publications (2)

Publication Number Publication Date
JP2017152570A JP2017152570A (ja) 2017-08-31
JP6759626B2 true JP6759626B2 (ja) 2020-09-23

Family

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JP2016034448A Active JP6759626B2 (ja) 2016-02-25 2016-02-25 エピタキシャルウェーハの製造方法およびエピタキシャルウェーハ

Country Status (5)

Country Link
JP (1) JP6759626B2 (zh)
KR (1) KR102129190B1 (zh)
CN (1) CN108885998B (zh)
TW (1) TWI643250B (zh)
WO (1) WO2017145470A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109192743A (zh) * 2018-09-04 2019-01-11 德淮半导体有限公司 图像传感器及其形成方法
CN114156383B (zh) * 2021-12-03 2024-06-21 扬州乾照光电有限公司 半导体器件及其制作方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2583803B2 (ja) * 1990-06-08 1997-02-19 東芝セラミックス株式会社 アモルファス構造を有するウェーハ
JP3384506B2 (ja) 1993-03-30 2003-03-10 ソニー株式会社 半導体基板の製造方法
JP2791429B2 (ja) * 1996-09-18 1998-08-27 工業技術院長 シリコンウェハーの常温接合法
US7910455B2 (en) * 2006-04-27 2011-03-22 Shin-Etsu Handotai Co., Ltd. Method for producing SOI wafer
JP2008198656A (ja) * 2007-02-08 2008-08-28 Shin Etsu Chem Co Ltd 半導体基板の製造方法
US7989305B2 (en) * 2007-10-10 2011-08-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate using cluster ion
JP2011054704A (ja) * 2009-09-01 2011-03-17 Sumco Corp 貼り合わせウェーハの製造方法
JP2012182201A (ja) * 2011-02-28 2012-09-20 Shin Etsu Chem Co Ltd 半導体ウェーハの製造方法
CN103534791B (zh) * 2011-05-13 2016-05-11 胜高股份有限公司 半导体外延晶片的制造方法、半导体外延晶片及固体摄像元件的制造方法
JP6229258B2 (ja) * 2012-11-13 2017-11-15 株式会社Sumco 貼り合わせウェーハの製造方法および貼り合わせウェーハ
JP6289805B2 (ja) * 2012-11-13 2018-03-07 株式会社Sumco 半導体エピタキシャルウェーハの製造方法、半導体エピタキシャルウェーハ、および固体撮像素子の製造方法
JP5799936B2 (ja) * 2012-11-13 2015-10-28 株式会社Sumco 半導体エピタキシャルウェーハの製造方法、半導体エピタキシャルウェーハ、および固体撮像素子の製造方法
JP5704155B2 (ja) * 2012-12-19 2015-04-22 株式会社Sumco エピタキシャルウェーハの製造方法
JP2014216555A (ja) * 2013-04-26 2014-11-17 株式会社豊田自動織機 半導体基板の製造方法
JP6065848B2 (ja) * 2014-01-07 2017-01-25 株式会社Sumco 半導体エピタキシャルウェーハの製造方法、半導体エピタキシャルウェーハ、および固体撮像素子の製造方法

Also Published As

Publication number Publication date
TWI643250B (zh) 2018-12-01
KR20180084086A (ko) 2018-07-24
TW201730930A (zh) 2017-09-01
CN108885998B (zh) 2023-06-16
JP2017152570A (ja) 2017-08-31
CN108885998A (zh) 2018-11-23
WO2017145470A1 (ja) 2017-08-31
KR102129190B1 (ko) 2020-07-01

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