JP6678506B2 - 半導体パッケージ及び半導体パッケージの製造方法 - Google Patents
半導体パッケージ及び半導体パッケージの製造方法 Download PDFInfo
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- JP6678506B2 JP6678506B2 JP2016090189A JP2016090189A JP6678506B2 JP 6678506 B2 JP6678506 B2 JP 6678506B2 JP 2016090189 A JP2016090189 A JP 2016090189A JP 2016090189 A JP2016090189 A JP 2016090189A JP 6678506 B2 JP6678506 B2 JP 6678506B2
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- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
- H10W20/042—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers
- H10W20/043—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroplating
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- H10W20/044—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers the barrier, adhesion or liner layers being seed or nucleation layers for electroless plating
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- H10W90/00—Package configurations
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- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Engineering & Computer Science (AREA)
- Structure Of Printed Boards (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Led Device Packages (AREA)
- Microelectronics & Electronic Packaging (AREA)
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016090189A JP6678506B2 (ja) | 2016-04-28 | 2016-04-28 | 半導体パッケージ及び半導体パッケージの製造方法 |
| TW110137066A TWI784738B (zh) | 2016-04-28 | 2017-03-10 | 半導體封裝件及半導體封裝件之製造方法 |
| TW106107950A TWI745359B (zh) | 2016-04-28 | 2017-03-10 | 半導體封裝件及半導體封裝件之製造方法 |
| US15/472,387 US10553456B2 (en) | 2016-04-28 | 2017-03-29 | Semiconductor package and manufacturing method of semiconductor package |
| CN202210347036.1A CN114823629A (zh) | 2016-04-28 | 2017-04-10 | 半导体封装件及半导体封装件的制造方法 |
| CN201710227962.4A CN107424980B (zh) | 2016-04-28 | 2017-04-10 | 半导体封装件及半导体封装件的制造方法 |
| KR1020170047733A KR20170123238A (ko) | 2016-04-28 | 2017-04-13 | 반도체 패키지 및 반도체 패키지의 제조 방법 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016090189A JP6678506B2 (ja) | 2016-04-28 | 2016-04-28 | 半導体パッケージ及び半導体パッケージの製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017199823A JP2017199823A (ja) | 2017-11-02 |
| JP2017199823A5 JP2017199823A5 (https=) | 2018-12-27 |
| JP6678506B2 true JP6678506B2 (ja) | 2020-04-08 |
Family
ID=60159087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016090189A Active JP6678506B2 (ja) | 2016-04-28 | 2016-04-28 | 半導体パッケージ及び半導体パッケージの製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US10553456B2 (https=) |
| JP (1) | JP6678506B2 (https=) |
| KR (1) | KR20170123238A (https=) |
| CN (2) | CN114823629A (https=) |
| TW (2) | TWI784738B (https=) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6691835B2 (ja) * | 2016-06-17 | 2020-05-13 | 株式会社アムコー・テクノロジー・ジャパン | 半導体パッケージの製造方法 |
| KR102138012B1 (ko) * | 2018-08-28 | 2020-07-27 | 삼성전자주식회사 | 팬-아웃 반도체 패키지 |
| CN111415908B (zh) | 2019-01-07 | 2022-02-22 | 台达电子企业管理(上海)有限公司 | 电源模块、芯片嵌入式封装模块及制备方法 |
| WO2021111517A1 (ja) * | 2019-12-03 | 2021-06-10 | 太陽誘電株式会社 | 部品モジュールおよびその製造方法 |
| US12266581B2 (en) * | 2020-10-30 | 2025-04-01 | Intel Corporation | Electronic substrates having heterogeneous dielectric layers |
| US20220238473A1 (en) * | 2021-01-25 | 2022-07-28 | Stmicroelectronics S.R.L. | Method of manufacturing semiconductor devices and corresponding semiconductor device |
Family Cites Families (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62163962A (ja) | 1986-01-14 | 1987-07-20 | Nec Corp | 超音波顕微鏡 |
| JPS62163962U (https=) * | 1986-04-08 | 1987-10-17 | ||
| JP3516592B2 (ja) * | 1998-08-18 | 2004-04-05 | 沖電気工業株式会社 | 半導体装置およびその製造方法 |
| US6426565B1 (en) * | 2000-03-22 | 2002-07-30 | International Business Machines Corporation | Electronic package and method of making same |
| JP3895570B2 (ja) * | 2000-12-28 | 2007-03-22 | 株式会社ルネサステクノロジ | 半導体装置 |
| JP5183583B2 (ja) * | 2000-12-28 | 2013-04-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP2003179193A (ja) * | 2001-12-12 | 2003-06-27 | Matsushita Electric Ind Co Ltd | リードフレームおよびその製造方法ならびに樹脂封止型半導体装置およびその製造方法ならびに樹脂封止型半導体装置の検査方法 |
| US8148803B2 (en) * | 2002-02-15 | 2012-04-03 | Micron Technology, Inc. | Molded stiffener for thin substrates |
| JP4093818B2 (ja) * | 2002-08-07 | 2008-06-04 | 三洋電機株式会社 | 半導体装置の製造方法 |
| JP3988679B2 (ja) * | 2003-05-26 | 2007-10-10 | カシオ計算機株式会社 | 半導体基板 |
| TWI249209B (en) * | 2004-12-22 | 2006-02-11 | Siliconware Precision Industries Co Ltd | Semiconductor package with support structure and fabrication method thereof |
| JP5017977B2 (ja) * | 2006-09-14 | 2012-09-05 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
| US20080083994A1 (en) * | 2006-10-06 | 2008-04-10 | Choon Hiang Lim | Method for producing a semiconductor component and substrate for carrying out the method |
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| US9452924B2 (en) * | 2012-06-15 | 2016-09-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | MEMS devices and fabrication methods thereof |
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| CN105280567B (zh) * | 2014-06-19 | 2018-12-28 | 株式会社吉帝伟士 | 半导体封装件及其制造方法 |
| US9315378B2 (en) * | 2014-08-12 | 2016-04-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods for packaging a microelectromechanical system (MEMS) wafer and application-specific integrated circuit (ASIC) dies using wire bonding |
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2016
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- 2017-04-10 CN CN202210347036.1A patent/CN114823629A/zh active Pending
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| JP2017199823A (ja) | 2017-11-02 |
| TWI745359B (zh) | 2021-11-11 |
| CN107424980B (zh) | 2022-04-15 |
| US10553456B2 (en) | 2020-02-04 |
| CN114823629A (zh) | 2022-07-29 |
| US20170316996A1 (en) | 2017-11-02 |
| TWI784738B (zh) | 2022-11-21 |
| TW202207380A (zh) | 2022-02-16 |
| TW201803036A (zh) | 2018-01-16 |
| KR20170123238A (ko) | 2017-11-07 |
| CN107424980A (zh) | 2017-12-01 |
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